tangxifan c2d8fa00ba add rr_block unique_side_module verilog generation		2019-06-04 17:47:40 -06:00
..
ARCH	Update spice path in architecture	2019-05-29 10:08:58 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	add rr_block unique_side_module verilog generation	2019-06-04 17:47:40 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	Add travis full path to avoid missing sources	2019-05-16 15:51:10 -06:00
.regression_verilog.sh	Test Cmake fix	2019-06-03 10:31:44 -06:00
CMakeLists.txt	Force graphics to false	2019-05-15 15:01:54 -06:00
Makefile	fixed bugs in CMakeLists.txt and Makefile	2019-05-03 23:03:04 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	add side mirror detection for RRSwitchBlock	2019-06-04 13:01:22 -06:00