ganeshgore c1b73efa62 Added support for simulation setting file in the task flow		2020-06-10 23:12:30 -06:00
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OpenFPGAShellScripts	BugFix : Relative path for refrence benchmark fixed	2020-04-25 20:16:17 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	add register chain and scan chain to Travis CI	2020-04-12 15:28:22 -06:00
arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
benchmarks	update microbenchmark and2 module name	2020-04-20 13:37:39 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Fixed modelsim include references	2020-04-24 21:53:57 -06:00
openfpga_arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
scripts	Added support for simulation setting file in the task flow	2020-06-10 23:12:30 -06:00
tasks	Added support for simulation setting file in the task flow	2020-06-10 23:12:30 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00