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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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c0e8d98c6f
OpenFPGA
/
vpr
/
src
History
tangxifan
28123b8052
remove the direct connected IPIN/OPIN from RR GSB builder
2020-03-21 11:38:39 -06:00
..
analysis
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00
base
fixed a bug in using tileable routing when directlist is enabled
2020-03-20 16:38:58 -06:00
device
adapt top function of tileable rr_graph builder
2020-03-06 15:24:26 -07:00
draw
correct missing rr_nodes usage to rr_graph obj
2020-02-04 16:48:15 -07:00
pack
fix dependency error in pack_types header file
2020-02-18 11:36:16 -07:00
place
bug fixing for heterogenenous FPGA when using the RRGraph object
2020-02-04 17:31:39 -07:00
power
power estimation adapted to use RRGraph object
2020-02-01 12:26:42 -07:00
route
critical bug fixed for tileable routing: delayless and wire2ipin switch was reverted
2020-03-20 17:23:19 -06:00
tileable_rr_graph
remove the direct connected IPIN/OPIN from RR GSB builder
2020-03-21 11:38:39 -06:00
timing
net delay adopt RRGraph object, compile with no errors
2020-02-01 22:38:21 -07:00
util
correct missing rr_nodes usage to rr_graph obj
2020-02-04 16:48:15 -07:00
main.cpp
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00