74 lines
2.8 KiB
C++
74 lines
2.8 KiB
C++
/***********************************************
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* This file includes functions to generate
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* Verilog submodules for wires.
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**********************************************/
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#include <string>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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/* Device-level header files */
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#include "module_manager.h"
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#include "module_manager_utils.h"
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#include "openfpga_naming.h"
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#include "build_wire_modules.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Print a Verilog module of a regular wire segment
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* Regular wire, which is 1-input and 1-output
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* This type of wires are used in the local routing architecture
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* +------+
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* input --->| wire |---> output
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* +------+
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*
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*******************************************************************/
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static
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void build_wire_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& wire_model) {
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/* Find the input port, output port*/
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
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std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
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/* Makre sure the port size is what we want */
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VTR_ASSERT (1 == input_ports.size());
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VTR_ASSERT (1 == output_ports.size());
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VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0]));
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VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0]));
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model);
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}
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/********************************************************************
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* This function will only create wire modules with a number of
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* ports that are defined by users.
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* It will NOT insert any internal logic, which should be handled
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* by Verilog/SPICE writers
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*******************************************************************/
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void build_wire_modules(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib) {
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vtr::ScopedStartFinishTimer timer("Build wire modules");
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/* Print Verilog models for regular wires*/
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for (const auto& wire_model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) {
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/* Bypass user-defined circuit models */
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if ( (!circuit_lib.model_circuit_netlist(wire_model).empty())
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&& (!circuit_lib.model_verilog_netlist(wire_model).empty()) ) {
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continue;
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}
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build_wire_module(module_manager, circuit_lib, wire_model);
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}
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}
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} /* end namespace openfpga */
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