112 lines
3.9 KiB
C++
112 lines
3.9 KiB
C++
/********************************************************************
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* This file includes functions that outputs a configuration protocol to XML
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*format
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*******************************************************************/
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/* Headers from system goes first */
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#include <algorithm>
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#include <string>
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/* Headers from vtr util library */
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#include "openfpga_digest.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from readarchopenfpga library */
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#include "config_protocol_xml_constants.h"
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#include "write_xml_config_protocol.h"
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#include "write_xml_utils.h"
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/********************************************************************
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* A writer to output a configuration memory organization to XML format
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*******************************************************************/
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static void write_xml_config_organization(std::fstream& fp, const char* fname,
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const ConfigProtocol& config_protocol,
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const CircuitLibrary& circuit_lib) {
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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fp << "\t\t"
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<< "<organization";
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write_xml_attribute(fp, "type",
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CONFIG_PROTOCOL_TYPE_STRING[config_protocol.type()]);
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write_xml_attribute(
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fp, "circuit_model_name",
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circuit_lib.model_name(config_protocol.memory_model()).c_str());
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write_xml_attribute(fp, XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR,
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config_protocol.num_regions());
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fp << "/>"
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<< "\n";
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/* CCFF protocol details */
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if (config_protocol.type() == CONFIG_MEM_SCAN_CHAIN) {
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for (openfpga::BasicPort port : config_protocol.prog_clock_pins()) {
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fp << "\t\t\t"
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<< "<" << XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME;
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write_xml_attribute(fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR,
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port.to_verilog_string().c_str());
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write_xml_attribute(
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fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR,
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config_protocol.prog_clock_pin_ccff_head_indices_str(port).c_str());
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fp << "/>"
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<< "\n";
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}
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}
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/* BL/WL protocol details */
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if (config_protocol.type() == CONFIG_MEM_QL_MEMORY_BANK) {
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fp << "\t\t\t"
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<< "<bl";
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write_xml_attribute(
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fp, "protocol",
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BLWL_PROTOCOL_TYPE_STRING[config_protocol.bl_protocol_type()]);
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write_xml_attribute(
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fp, "circuit_model_name",
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circuit_lib.model_name(config_protocol.bl_memory_model()).c_str());
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write_xml_attribute(fp, "num_banks", config_protocol.bl_num_banks());
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fp << "/>"
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<< "\n";
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fp << "\t\t\t"
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<< "<wl";
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write_xml_attribute(
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fp, "protocol",
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BLWL_PROTOCOL_TYPE_STRING[config_protocol.wl_protocol_type()]);
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write_xml_attribute(
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fp, "circuit_model_name",
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circuit_lib.model_name(config_protocol.wl_memory_model()).c_str());
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write_xml_attribute(fp, "num_banks", config_protocol.wl_num_banks());
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fp << "/>"
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<< "\n";
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}
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fp << "\t"
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<< "</organization>"
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<< "\n";
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}
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/********************************************************************
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* A writer to output a configuration protocol to XML format
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* Note:
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* This function should be run AFTER the function
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* link_config_protocol_to_circuit_library()
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*******************************************************************/
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void write_xml_config_protocol(std::fstream& fp, const char* fname,
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const ConfigProtocol& config_protocol,
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const CircuitLibrary& circuit_lib) {
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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/* Write the root node */
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fp << "\t"
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<< "<configuration_protocol>"
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<< "\n";
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/* Write configuration memory organization */
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write_xml_config_organization(fp, fname, config_protocol, circuit_lib);
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/* Finish writing the root node */
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fp << "\t"
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<< "</configuration_protocol>"
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<< "\n";
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}
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