275 lines
7.7 KiB
Verilog
275 lines
7.7 KiB
Verilog
//-----------------------------------------------------
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// Design Name : frac_lut4_arith
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// File Name : frac_lut4_arith.v
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// Function : 4-input Look Up Table with integrated carry logic
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// - mode_bit[0] switch between arithmetic mode and LUT mode
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// - mode_bit[1] switch between regular LUT mode and fracturable
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// mode
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// Note : The HDL is a technology mapped netlist based on the Skywater
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// 130nm High-Density cell library.
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// TODO: Create a behavioral HDL version so that we are portable
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// between PDKs
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// Coder : Xifan TANG
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//-----------------------------------------------------
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module frac_lut4_arith (
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input [0:3] in,
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input [0:0] cin,
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output [0:1] lut3_out,
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output [0:0] lut4_out,
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output [0:0] cout,
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input [0:15] sram,
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input [0:1] mode);
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//----- BEGIN wire-connection ports -----
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wire [0:3] in;
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wire [0:0] cin;
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wire [0:1] lut2_out;
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wire [0:1] lut3_out;
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wire [0:0] lut4_out;
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wire [0:0] cout;
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wire [0:0] arith_in2;
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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wire [0:0] sky130_fd_sc_hd__buf_2_0_X;
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wire [0:0] sky130_fd_sc_hd__buf_2_1_X;
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wire [0:0] sky130_fd_sc_hd__buf_2_2_X;
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wire [0:0] sky130_fd_sc_hd__buf_2_3_X;
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wire [0:0] sky130_fd_sc_hd__inv_1_0_Y;
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wire [0:0] sky130_fd_sc_hd__inv_1_1_Y;
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wire [0:0] sky130_fd_sc_hd__inv_1_2_Y;
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wire [0:0] sky130_fd_sc_hd__inv_1_3_Y;
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wire [0:0] sky130_fd_sc_hd__or2_1_0_X;
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ (
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.A(mode[1]),
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.B(in[3]),
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.X(sky130_fd_sc_hd__or2_1_0_X[0]));
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sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
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.A(in[0]),
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.Y(sky130_fd_sc_hd__inv_1_0_Y[0]));
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sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ (
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.A(in[1]),
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.Y(sky130_fd_sc_hd__inv_1_1_Y[0]));
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assign arith_in2 = mode[0] ? in[2] : cin;
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sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ (
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.A(arith_in2),
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.Y(sky130_fd_sc_hd__inv_1_2_Y[0]));
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sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
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.A(sky130_fd_sc_hd__or2_1_0_X[0]),
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.Y(sky130_fd_sc_hd__inv_1_3_Y[0]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
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.A(in[0]),
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.X(sky130_fd_sc_hd__buf_2_0_X[0]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
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.A(in[1]),
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.X(sky130_fd_sc_hd__buf_2_1_X[0]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
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.A(in[2]),
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.X(sky130_fd_sc_hd__buf_2_2_X[0]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
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.A(sky130_fd_sc_hd__or2_1_0_X[0]),
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.X(sky130_fd_sc_hd__buf_2_3_X[0]));
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frac_lut4_mux frac_lut4_mux_0_ (
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.in(sram[0:15]),
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.sram({sky130_fd_sc_hd__buf_2_0_X[0], sky130_fd_sc_hd__buf_2_1_X[0], sky130_fd_sc_hd__buf_2_2_X[0], sky130_fd_sc_hd__buf_2_3_X[0]}),
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.sram_inv({sky130_fd_sc_hd__inv_1_0_Y[0], sky130_fd_sc_hd__inv_1_1_Y[0], sky130_fd_sc_hd__inv_1_2_Y[0], sky130_fd_sc_hd__inv_1_3_Y[0]}),
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.lut2_out(lut2_out[0:1]),
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.lut3_out(lut3_out[0:1]),
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.lut4_out(lut4_out[0]));
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assign cout = lut2_out[0] ? cin : lut2_out[1];
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endmodule
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// ----- Verilog module for frac_lut4_mux -----
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module frac_lut4_mux(in,
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sram,
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sram_inv,
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lut2_out,
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lut3_out,
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lut4_out);
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//----- INPUT PORTS -----
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input [0:15] in;
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//----- INPUT PORTS -----
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input [0:3] sram;
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//----- INPUT PORTS -----
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input [0:3] sram_inv;
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//----- OUTPUT PORTS -----
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output [0:1] lut2_out;
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//----- OUTPUT PORTS -----
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output [0:1] lut3_out;
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//----- OUTPUT PORTS -----
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output [0:0] lut4_out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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wire [0:0] sky130_fd_sc_hd__buf_2_5_X;
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wire [0:0] sky130_fd_sc_hd__buf_2_6_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_10_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_11_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_12_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_13_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_14_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
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wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
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.A(sky130_fd_sc_hd__mux2_1_10_X[0]),
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.X(lut2_out[0]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
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.A(sky130_fd_sc_hd__mux2_1_11_X[0]),
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.X(lut2_out[1]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
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.A(sky130_fd_sc_hd__mux2_1_12_X[0]),
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.X(lut3_out[0]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
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.A(sky130_fd_sc_hd__mux2_1_13_X[0]),
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.X(lut3_out[1]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ (
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.A(sky130_fd_sc_hd__mux2_1_14_X[0]),
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.X(lut4_out[0]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ (
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.A(sky130_fd_sc_hd__mux2_1_8_X[0]),
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.X(sky130_fd_sc_hd__buf_2_5_X[0]));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ (
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.A(sky130_fd_sc_hd__mux2_1_9_X[0]),
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.X(sky130_fd_sc_hd__buf_2_6_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
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.A1(in[0]),
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.A0(in[1]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_0_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
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.A1(in[2]),
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.A0(in[3]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_1_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ (
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.A1(in[4]),
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.A0(in[5]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_2_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ (
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.A1(in[6]),
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.A0(in[7]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_3_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ (
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.A1(in[8]),
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.A0(in[9]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_4_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ (
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.A1(in[10]),
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.A0(in[11]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_5_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ (
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.A1(in[12]),
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.A0(in[13]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_6_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ (
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.A1(in[14]),
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.A0(in[15]),
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.S(sram[0]),
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.X(sky130_fd_sc_hd__mux2_1_7_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_0_X[0]),
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.A0(sky130_fd_sc_hd__mux2_1_1_X[0]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_8_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
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.A1(sky130_fd_sc_hd__mux2_1_2_X[0]),
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.A0(sky130_fd_sc_hd__mux2_1_3_X[0]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_9_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
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.A1(sky130_fd_sc_hd__mux2_1_4_X[0]),
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.A0(sky130_fd_sc_hd__mux2_1_5_X[0]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_10_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
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.A1(sky130_fd_sc_hd__mux2_1_6_X[0]),
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.A0(sky130_fd_sc_hd__mux2_1_7_X[0]),
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.S(sram[1]),
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.X(sky130_fd_sc_hd__mux2_1_11_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
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.A1(sky130_fd_sc_hd__buf_2_5_X[0]),
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.A0(sky130_fd_sc_hd__buf_2_6_X[0]),
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.S(sram[2]),
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.X(sky130_fd_sc_hd__mux2_1_12_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
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.A1(sky130_fd_sc_hd__mux2_1_10_X[0]),
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.A0(sky130_fd_sc_hd__mux2_1_11_X[0]),
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.S(sram[2]),
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.X(sky130_fd_sc_hd__mux2_1_13_X[0]));
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sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
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.A1(sky130_fd_sc_hd__mux2_1_12_X[0]),
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.A0(sky130_fd_sc_hd__mux2_1_13_X[0]),
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.S(sram[3]),
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.X(sky130_fd_sc_hd__mux2_1_14_X[0]));
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endmodule
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// ----- END Verilog module for frac_lut4_mux -----
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