107 lines
2.6 KiB
Verilog
107 lines
2.6 KiB
Verilog
/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */
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module s298(clock, G0, G1, G2, G117, G132, G66, G118, G133, G67);
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input G0;
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input G1;
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(* init = 1'h0 *)
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reg G10 = 1'h0;
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(* init = 1'h0 *)
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reg G11 = 1'h0;
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(* init = 1'h0 *)
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output G117;
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reg G117 = 1'h0;
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(* init = 1'h0 *)
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output G118;
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reg G118 = 1'h0;
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(* init = 1'h0 *)
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reg G12 = 1'h0;
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(* init = 1'h0 *)
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reg G13 = 1'h0;
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(* init = 1'h0 *)
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output G132;
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reg G132 = 1'h0;
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(* init = 1'h0 *)
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output G133;
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reg G133 = 1'h0;
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(* init = 1'h0 *)
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reg G14 = 1'h0;
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(* init = 1'h0 *)
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reg G15 = 1'h0;
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input G2;
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(* init = 1'h0 *)
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reg G22 = 1'h0;
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(* init = 1'h0 *)
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reg G23 = 1'h0;
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(* init = 1'h0 *)
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output G66;
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reg G66 = 1'h0;
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(* init = 1'h0 *)
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output G67;
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reg G67 = 1'h0;
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input clock;
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wire n21;
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wire n26;
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wire n31;
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wire n36;
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wire n41;
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wire n46;
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wire n51;
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wire n55;
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wire n56;
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wire n57;
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wire n59;
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wire n59_1;
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wire n63;
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wire n65;
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wire n67;
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wire n71;
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wire n75;
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wire n80;
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always @(posedge clock)
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G10 <= n21;
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always @(posedge clock)
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G118 <= n63;
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always @(posedge clock)
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G132 <= n67;
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always @(posedge clock)
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G133 <= n71;
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always @(posedge clock)
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G22 <= n75;
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always @(posedge clock)
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G23 <= n80;
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always @(posedge clock)
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G11 <= n26;
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always @(posedge clock)
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G12 <= n31;
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always @(posedge clock)
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G13 <= n36;
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always @(posedge clock)
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G14 <= n41;
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always @(posedge clock)
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G15 <= n46;
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always @(posedge clock)
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G66 <= n51;
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always @(posedge clock)
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G67 <= n55;
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always @(posedge clock)
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G117 <= n59;
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assign n63 = 8'h8d >> { G10, n57, n56 };
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assign n56 = 64'h55555555555545d5 >> { G12, G14, G22, G13, G11, G15 };
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assign n57 = 32'd3963940422 >> { G11, G118, G12, G13, G14 };
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assign n67 = 8'h8d >> { G10, n59_1, n56 };
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assign n59_1 = 32'd2818615810 >> { G11, G132, G12, G13, G14 };
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assign n21 = 4'h1 >> { G10, G0 };
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assign n26 = 32'd100926982 >> { G13, G12, G0, G11, G10 };
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assign n31 = 16'h1222 >> { G10, G11, G0, G12 };
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assign n36 = 32'd304095778 >> { G10, G12, G11, G0, G13 };
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assign n41 = 8'h09 >> { G0, G14, n65 };
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assign n65 = 32'd1431655701 >> { G12, G11, G13, G10, G23 };
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assign n46 = 4'h1 >> { n56, G0 };
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assign n51 = 32'd2323679744 >> { G12, G13, G14, G66, n56 };
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assign n55 = 64'ha0a20002a2822202 >> { G12, G67, G11, G14, G13, n56 };
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assign n59 = 64'ha022a222a0228022 >> { G11, G12, G14, G117, G13, n56 };
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assign n71 = 64'h88a0002088800000 >> { G11, G133, G13, G12, G14, n56 };
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assign n75 = 8'h06 >> { G0, G22, G2 };
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assign n80 = 8'h06 >> { G0, G23, G1 };
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endmodule
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