574 lines
28 KiB
C++
574 lines
28 KiB
C++
/********************************************************************
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* This file includes functions that are used to annotate pb_graph_node
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* and pb_graph_pins from VPR to OpenFPGA
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "pb_type_utils.h"
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#include "pb_graph_utils.h"
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#include "annotate_pb_graph.h"
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#include "check_pb_graph_annotation.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* This function will recursively walk through all the pb_graph nodes
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* starting from a top node.
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* It aims to annotate the physical type of each interconnect.
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* This is due to that the type of interconnect 'complete' may diverge
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* in physical implmentation.
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* - When there is only one input driving a 'complete' interconnection,
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* it will be implemented with wires
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* - When there are multiple inputs driving a 'complete' interconnection,
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* it will be implemented with routing multiplexers
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*******************************************************************/
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static
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void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_node* pb_graph_node,
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VprDeviceAnnotation& vpr_device_annotation,
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const bool& verbose_output) {
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/* Skip the root node because we start from the inputs of child pb_graph node
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*
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* pb_graph_node
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* +----------------------------------
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* | child_pb_graph_node
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* | +-----------------
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* | |
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* |-------------+-->input_pins
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* | |
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* |-------------+-->clock_pins
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* |
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*
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*/
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if (false == pb_graph_node->is_root()) {
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/* We only care the physical modes! But we have to find it through the parent node */
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t_mode* child_physical_mode = vpr_device_annotation.physical_mode(pb_graph_node->parent_pb_graph_node->pb_type);
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VTR_ASSERT(nullptr != child_physical_mode);
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std::map<t_interconnect*, size_t> interc_num_inputs;
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/* Find all the interconnects sourced from the input and clock pins */
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for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
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for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
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for (int iedge = 0; iedge < pb_graph_node->input_pins[iport][ipin].num_input_edges; ++iedge) {
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t_interconnect* interc = pb_graph_node->input_pins[iport][ipin].input_edges[iedge]->interconnect;
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/* Ensure that the interconnect is unique in the list */
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if (0 < interc_num_inputs.count(interc)) {
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continue;
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}
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/* Unique interconnect, initialize the counter to be zero */
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interc_num_inputs[interc] = 0;
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}
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}
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}
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for (int iport = 0; iport < pb_graph_node->num_clock_ports; ++iport) {
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for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) {
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for (int iedge = 0; iedge < pb_graph_node->clock_pins[iport][ipin].num_input_edges; ++iedge) {
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t_interconnect* interc = pb_graph_node->clock_pins[iport][ipin].input_edges[iedge]->interconnect;
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/* Ensure that the interconnect is unique in the list */
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if (0 < interc_num_inputs.count(interc)) {
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continue;
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}
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/* Unique interconnect, initialize the counter to be zero */
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interc_num_inputs[interc] = 0;
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}
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}
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}
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/* Check: all the element should be initialized to 0 */
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for (const auto& pair : interc_num_inputs) {
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VTR_ASSERT(nullptr != pair.first);
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VTR_ASSERT(0 == pair.second);
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}
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/* We only care input and clock pins */
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for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
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for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
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/* For each interconnect, we count the total number of inputs */
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for (const auto& pair : interc_num_inputs) {
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interc_num_inputs[pair.first] += pb_graph_pin_inputs(&(pb_graph_node->input_pins[iport][ipin]), pair.first).size();
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}
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}
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}
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for (int iport = 0; iport < pb_graph_node->num_clock_ports; ++iport) {
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for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) {
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/* For each interconnect, we count the total number of inputs */
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for (const auto& pair : interc_num_inputs) {
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interc_num_inputs[pair.first] += pb_graph_pin_inputs(&(pb_graph_node->clock_pins[iport][ipin]), pair.first).size();
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}
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}
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}
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/* For each interconnect that has more than 1 input, we can infer the physical type */
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for (const auto& pair : interc_num_inputs) {
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t_interconnect* interc = pair.first;
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size_t actual_interc_num_inputs = pair.second;
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/* If the number inputs for an interconnect is zero, this is a 0-driver pin
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* we just set 1 to use direct wires
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*/
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if (0 == actual_interc_num_inputs) {
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actual_interc_num_inputs = 1;
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}
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e_interconnect interc_physical_type = pb_interconnect_physical_type(interc, actual_interc_num_inputs);
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if (interc_physical_type == vpr_device_annotation.interconnect_physical_type(interc)) {
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/* Skip annotation if we have already done! */
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continue;
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}
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VTR_LOGV(verbose_output,
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"Infer physical type '%s' of interconnect '%s' (was '%s')\n",
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INTERCONNECT_TYPE_STRING[interc_physical_type],
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interc->name,
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INTERCONNECT_TYPE_STRING[interc->type]);
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vpr_device_annotation.add_interconnect_physical_type(interc, interc_physical_type);
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}
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}
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/* If we reach a primitive pb_graph node, we return */
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if (true == is_primitive_pb_type(pb_graph_node->pb_type)) {
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return;
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}
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/* Find the physical mode of current pb_graph node */
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t_mode* physical_mode = vpr_device_annotation.physical_mode(pb_graph_node->pb_type);
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VTR_ASSERT(nullptr != physical_mode);
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/* Before going recursive, we should check the interconnect between output pins
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* Note that this is NOT applicable to primitive pb_graph nodes!!!
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*
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* pb_graph_node
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* -------------------------------+
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* |
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* child_pb_graph_node |
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* -------------------+ |
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* | |
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* output_pin +<----------+ output_pin
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* | |
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* -------------------+ |
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*
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*/
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{ /* Use a code block to use local variables freely */
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std::map<t_interconnect*, size_t> interc_num_inputs;
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/* Find all the interconnects sourced from the output pins */
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for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
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for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
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for (int iedge = 0; iedge < pb_graph_node->output_pins[iport][ipin].num_input_edges; ++iedge) {
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t_interconnect* interc = pb_graph_node->output_pins[iport][ipin].input_edges[iedge]->interconnect;
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/* Ensure that the interconnect is unique in the list */
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if (0 < interc_num_inputs.count(interc)) {
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continue;
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}
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/* Unique interconnect, initialize the counter to be zero */
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interc_num_inputs[interc] = 0;
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}
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}
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}
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/* Check: all the element should be initialized to 0 */
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for (const auto& pair : interc_num_inputs) {
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VTR_ASSERT(nullptr != pair.first);
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VTR_ASSERT(0 == pair.second);
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}
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/* We only care input and clock pins */
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for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
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for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
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/* For each interconnect, we count the total number of inputs */
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for (const auto& pair : interc_num_inputs) {
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interc_num_inputs[pair.first] += pb_graph_pin_inputs(&(pb_graph_node->output_pins[iport][ipin]), pair.first).size();
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}
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}
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}
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/* For each interconnect that has more than 1 input, we can infer the physical type */
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for (const auto& pair : interc_num_inputs) {
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t_interconnect* interc = pair.first;
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size_t actual_interc_num_inputs = pair.second;
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/* If the number inputs for an interconnect is zero, this is a 0-driver pin
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* we just set 1 to use direct wires
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*/
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if (0 == actual_interc_num_inputs) {
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actual_interc_num_inputs = 1;
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}
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e_interconnect interc_physical_type = pb_interconnect_physical_type(interc, actual_interc_num_inputs);
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if (interc_physical_type == vpr_device_annotation.interconnect_physical_type(interc)) {
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/* Skip annotation if we have already done! */
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continue;
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}
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VTR_LOGV(verbose_output,
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"Infer physical type '%s' of interconnect '%s' (was '%s')\n",
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INTERCONNECT_TYPE_STRING[interc_physical_type],
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interc->name,
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INTERCONNECT_TYPE_STRING[interc->type]);
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vpr_device_annotation.add_interconnect_physical_type(interc, interc_physical_type);
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}
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}
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/* Recursively visit all the child pb_graph_nodes */
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for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
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/* Each child may exist multiple times in the hierarchy*/
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for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
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rec_build_vpr_pb_graph_interconnect_physical_type_annotation(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
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vpr_device_annotation,
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verbose_output);
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}
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}
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}
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/********************************************************************
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* This function aims to annotate the physical type for each interconnect
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* inside the pb_graph
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*
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* Note:
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* - This function should be executed AFTER functions
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* build_vpr_physical_pb_mode_explicit_annotation()
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* build_vpr_physical_pb_mode_implicit_annotation()
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*******************************************************************/
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void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_device_ctx,
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VprDeviceAnnotation& vpr_device_annotation,
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const bool& verbose_output) {
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for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
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/* By pass nullptr for pb_graph head */
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if (nullptr == lb_type.pb_graph_head) {
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continue;
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}
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rec_build_vpr_pb_graph_interconnect_physical_type_annotation(lb_type.pb_graph_head, vpr_device_annotation, verbose_output);
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}
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}
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/********************************************************************
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* This function will recursively walk through all the pb_graph nodes
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* starting from a top node.
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* It aims to give an unique index to each pb_graph node
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*
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* Therefore, the sequence in visiting the nodes is critical
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* Here, we will follow the strategy where primitive nodes are visited first
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*******************************************************************/
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static
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void rec_build_vpr_primitive_pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node,
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VprDeviceAnnotation& vpr_device_annotation) {
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/* Go recursive first until we touch the primitive node */
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if (false == is_primitive_pb_type(pb_graph_node->pb_type)) {
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for (int imode = 0; imode < pb_graph_node->pb_type->num_modes; ++imode) {
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for (int ipb = 0; ipb < pb_graph_node->pb_type->modes[imode].num_pb_type_children; ++ipb) {
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/* Each child may exist multiple times in the hierarchy*/
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for (int jpb = 0; jpb < pb_graph_node->pb_type->modes[imode].pb_type_children[ipb].num_pb; ++jpb) {
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rec_build_vpr_primitive_pb_graph_node_unique_index(&(pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]),
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vpr_device_annotation);
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}
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}
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}
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return;
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}
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/* Give a unique index to the pb_graph_node */
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vpr_device_annotation.add_pb_graph_node_unique_index(pb_graph_node);
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}
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/********************************************************************
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* This function aims to assign an unique index to each
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* primitive pb_graph_node by following a recursive way in walking
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* through the pb_graph
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*
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* Note:
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* - The unique index is different from the placement_index in VPR's
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* pb_graph_node data structure. The placement index is only unique
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* for a node under its parent node. If the parent node is duplicated
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* across the graph, the placement index is not unique.
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* For example, a CLB contains 10 LEs and each of LE contains 2 LUTs
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* Inside each LE, the placement index of the LUTs are 0 and 1 respectively.
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* But these indices are not unique in the graph, as there are 20 LUTs in total
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*******************************************************************/
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static
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void annotate_primitive_pb_graph_node_unique_index(const DeviceContext& vpr_device_ctx,
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VprDeviceAnnotation& vpr_device_annotation) {
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for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
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/* By pass nullptr for pb_graph head */
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if (nullptr == lb_type.pb_graph_head) {
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continue;
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}
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rec_build_vpr_primitive_pb_graph_node_unique_index(lb_type.pb_graph_head, vpr_device_annotation);
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}
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}
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/********************************************************************
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* Evaluate if the two pb_graph pins are matched by
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* - pb_type port annotation
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* - LSB/MSB and pin offset
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*******************************************************************/
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static
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bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
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t_pb_graph_pin* physical_pb_graph_pin,
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const VprDeviceAnnotation& vpr_device_annotation) {
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/* If the parent ports of the two pins are not paired, fail */
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if (physical_pb_graph_pin->port != vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
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return false;
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}
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/* Check the pin number of physical pb_graph_pin matches the pin number of
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* operating pb_graph_pin plus a rotation offset
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* operating port physical port
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* LSB port_range.lsb() pin_number pin_number MSB
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* | | |
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* Operating port | | +------ |
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* | |<----offset--->|
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* Physical port | + + +
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*
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* Note:
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* - accumulated offset is NOT the pin rotate offset specified by users
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* It is an aggregation of the offset during pin pairing
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* Each time, we manage to pair two pins, the accumulated offset will be incremented
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* by the pin rotate offset value
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* The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
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*/
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int acc_offset = vpr_device_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port);
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const BasicPort& physical_port_range = vpr_device_annotation.physical_pb_port_range(operating_pb_graph_pin->port);
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if (physical_pb_graph_pin->pin_number != operating_pb_graph_pin->pin_number
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+ (int)physical_port_range.get_lsb()
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+ acc_offset) {
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return false;
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}
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/* Reach here, it means all the requirements have been met */
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return true;
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}
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/********************************************************************
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* A function to print message to log file/screen when physical pb_graph_pin
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* binding succeed
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*******************************************************************/
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static
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void print_success_bind_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
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t_pb_graph_pin* physical_pb_graph_pin) {
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VTR_LOG("Bind a pb_graph_node '%s[%d]' pin '%s[%d]' to a pb_graph_node '%s[%d]' pin '%s[%d]'!\n",
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operating_pb_graph_pin->parent_node->pb_type->name,
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operating_pb_graph_pin->parent_node->placement_index,
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operating_pb_graph_pin->port->name,
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operating_pb_graph_pin->pin_number,
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physical_pb_graph_pin->parent_node->pb_type->name,
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physical_pb_graph_pin->parent_node->placement_index,
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physical_pb_graph_pin->port->name,
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physical_pb_graph_pin->pin_number);
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}
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/********************************************************************
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* Bind a pb_graph_pin from an operating pb_graph_node to
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* a pb_graph_pin from a physical pb_graph_node
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* - the name matching rules are already defined in the vpr_device_annotation
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*******************************************************************/
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static
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void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
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t_pb_graph_node* physical_pb_graph_node,
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VprDeviceAnnotation& vpr_device_annotation,
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const bool& verbose_output) {
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/* Iterate over every port and pin of the operating pb_graph_node
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* and find the physical pins
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*/
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for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
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for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
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if (false == try_match_pb_graph_pin(operating_pb_graph_pin,
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&(physical_pb_graph_node->input_pins[iport][ipin]),
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vpr_device_annotation)) {
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continue;
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}
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/* Reach here, it means the pins are matched by the annotation requirements
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* We can pair the pin and return
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*/
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vpr_device_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->input_pins[iport][ipin]));
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if (true == verbose_output) {
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print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_device_annotation.physical_pb_graph_pin(operating_pb_graph_pin));
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}
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return;
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}
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}
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for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) {
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for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
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if (false == try_match_pb_graph_pin(operating_pb_graph_pin,
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&(physical_pb_graph_node->output_pins[iport][ipin]),
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vpr_device_annotation)) {
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continue;
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}
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/* Reach here, it means the pins are matched by the annotation requirements
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* We can pair the pin and return
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*/
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vpr_device_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->output_pins[iport][ipin]));
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if (true == verbose_output) {
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print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_device_annotation.physical_pb_graph_pin(operating_pb_graph_pin));
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}
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return;
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}
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}
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for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) {
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for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) {
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if (false == try_match_pb_graph_pin(operating_pb_graph_pin,
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&(physical_pb_graph_node->clock_pins[iport][ipin]),
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vpr_device_annotation)) {
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continue;
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}
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/* Reach here, it means the pins are matched by the annotation requirements
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* We can pair the pin and return
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*/
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|
vpr_device_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->clock_pins[iport][ipin]));
|
|
if (true == verbose_output) {
|
|
print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_device_annotation.physical_pb_graph_pin(operating_pb_graph_pin));
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* If we reach here, it means that pin pairing fails, error out! */
|
|
VTR_LOG_ERROR("Fail to match a physical pin for '%s' from pb_graph_node '%s'!\n",
|
|
operating_pb_graph_pin->port->name,
|
|
physical_pb_graph_node->hierarchical_type_name().c_str());
|
|
}
|
|
|
|
/********************************************************************
|
|
* This function will try bind each pin of the operating pb_graph_node
|
|
* to a pin of the physical pb_graph_node by following the annotation
|
|
* available in vpr_device_annotation
|
|
* It will add the pin bindings to the vpr_device_annotation
|
|
*******************************************************************/
|
|
static
|
|
void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_node,
|
|
t_pb_graph_node* physical_pb_graph_node,
|
|
VprDeviceAnnotation& vpr_device_annotation,
|
|
const bool& verbose_output) {
|
|
/* Iterate over every port and pin of the operating pb_graph_node
|
|
* and find the physical pins
|
|
*/
|
|
for (int iport = 0; iport < operating_pb_graph_node->num_input_ports; ++iport) {
|
|
for (int ipin = 0; ipin < operating_pb_graph_node->num_input_pins[iport]; ++ipin) {
|
|
annotate_physical_pb_graph_pin(&(operating_pb_graph_node->input_pins[iport][ipin]),
|
|
physical_pb_graph_node, vpr_device_annotation,
|
|
verbose_output);
|
|
}
|
|
}
|
|
|
|
for (int iport = 0; iport < operating_pb_graph_node->num_output_ports; ++iport) {
|
|
for (int ipin = 0; ipin < operating_pb_graph_node->num_output_pins[iport]; ++ipin) {
|
|
annotate_physical_pb_graph_pin(&(operating_pb_graph_node->output_pins[iport][ipin]),
|
|
physical_pb_graph_node, vpr_device_annotation,
|
|
verbose_output);
|
|
}
|
|
}
|
|
|
|
for (int iport = 0; iport < operating_pb_graph_node->num_clock_ports; ++iport) {
|
|
for (int ipin = 0; ipin < operating_pb_graph_node->num_clock_pins[iport]; ++ipin) {
|
|
annotate_physical_pb_graph_pin(&(operating_pb_graph_node->clock_pins[iport][ipin]),
|
|
physical_pb_graph_node, vpr_device_annotation,
|
|
verbose_output);
|
|
}
|
|
}
|
|
}
|
|
|
|
/********************************************************************
|
|
* This function will recursively walk through all the pb_graph nodes
|
|
* starting from a top node.
|
|
* It aims to give an unique index to each pb_graph node
|
|
*
|
|
* Therefore, the sequence in visiting the nodes is critical
|
|
* Here, we will follow the strategy where primitive nodes are visited first
|
|
*******************************************************************/
|
|
static
|
|
void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_node,
|
|
VprDeviceAnnotation& vpr_device_annotation,
|
|
const bool& verbose_output) {
|
|
/* Go recursive first until we touch the primitive node */
|
|
if (false == is_primitive_pb_type(pb_graph_node->pb_type)) {
|
|
for (int imode = 0; imode < pb_graph_node->pb_type->num_modes; ++imode) {
|
|
for (int ipb = 0; ipb < pb_graph_node->pb_type->modes[imode].num_pb_type_children; ++ipb) {
|
|
/* Each child may exist multiple times in the hierarchy*/
|
|
for (int jpb = 0; jpb < pb_graph_node->pb_type->modes[imode].pb_type_children[ipb].num_pb; ++jpb) {
|
|
rec_build_vpr_physical_pb_graph_node_annotation(&(pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]),
|
|
vpr_device_annotation,
|
|
verbose_output);
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* To bind operating pb_graph_node to their physical pb_graph_node:
|
|
* - Get the physical pb_type that this type of pb_graph_node should be mapped to
|
|
* - Calculate the unique index of physical pb_graph_node to which
|
|
* this pb_graph_node should be binded
|
|
* - Find the physical pb_graph_node with the given index
|
|
* To bind pins from operating pb_graph_node to their physical pb_graph_node pins
|
|
*/
|
|
t_pb_type* physical_pb_type = vpr_device_annotation.physical_pb_type(pb_graph_node->pb_type);
|
|
VTR_ASSERT(nullptr != physical_pb_type);
|
|
|
|
/* Index inference:
|
|
* physical_pb_graph_node_unique_index = operating_pb_graph_node_unique_index * factor + offset
|
|
* where factor and offset are provided by users
|
|
*/
|
|
PbGraphNodeId physical_pb_graph_node_id = PbGraphNodeId(
|
|
vpr_device_annotation.physical_pb_type_index_factor(pb_graph_node->pb_type)
|
|
* (size_t)vpr_device_annotation.pb_graph_node_unique_index(pb_graph_node)
|
|
+ vpr_device_annotation.physical_pb_type_index_offset(pb_graph_node->pb_type)
|
|
);
|
|
|
|
t_pb_graph_node* physical_pb_graph_node = vpr_device_annotation.pb_graph_node(physical_pb_type, physical_pb_graph_node_id);
|
|
VTR_ASSERT(nullptr != physical_pb_graph_node);
|
|
vpr_device_annotation.add_physical_pb_graph_node(pb_graph_node, physical_pb_graph_node);
|
|
|
|
VTR_LOGV(verbose_output,
|
|
"Bind operating pb_graph_node '%s' to physical pb_graph_node '%s'\n",
|
|
pb_graph_node->hierarchical_type_name().c_str(),
|
|
physical_pb_graph_node->hierarchical_type_name().c_str());
|
|
|
|
/* Try to bind each pins under this pb_graph_node to physical_pb_graph_node */
|
|
annotate_physical_pb_graph_node_pins(pb_graph_node, physical_pb_graph_node, vpr_device_annotation, verbose_output);
|
|
}
|
|
|
|
/********************************************************************
|
|
* Find the physical pb_graph_node for each primitive pb_graph_node
|
|
* - Bind operating pb_graph_node to their physical pb_graph_node
|
|
* - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
|
|
*******************************************************************/
|
|
static
|
|
void annotate_physical_pb_graph_node(const DeviceContext& vpr_device_ctx,
|
|
VprDeviceAnnotation& vpr_device_annotation,
|
|
const bool& verbose_output) {
|
|
for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
|
|
/* By pass nullptr for pb_graph head */
|
|
if (nullptr == lb_type.pb_graph_head) {
|
|
continue;
|
|
}
|
|
rec_build_vpr_physical_pb_graph_node_annotation(lb_type.pb_graph_head, vpr_device_annotation, verbose_output);
|
|
}
|
|
}
|
|
|
|
/********************************************************************
|
|
* Top-level function to annotate all the pb_graph nodes and pins
|
|
* - Give unique index to each primitive node in the same type
|
|
* - Bind operating pb_graph_node to their physical pb_graph_node
|
|
* - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
|
|
*******************************************************************/
|
|
void annotate_pb_graph(const DeviceContext& vpr_device_ctx,
|
|
VprDeviceAnnotation& vpr_device_annotation,
|
|
const bool& verbose_output) {
|
|
|
|
VTR_LOG("Assigning unique indices for primitive pb_graph nodes...");
|
|
VTR_LOGV(verbose_output, "\n");
|
|
annotate_primitive_pb_graph_node_unique_index(vpr_device_ctx, vpr_device_annotation);
|
|
VTR_LOG("Done\n");
|
|
|
|
VTR_LOG("Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...");
|
|
VTR_LOGV(verbose_output, "\n");
|
|
annotate_physical_pb_graph_node(vpr_device_ctx, vpr_device_annotation, verbose_output);
|
|
VTR_LOG("Done\n");
|
|
|
|
/* Check each primitive pb_graph_node and pin has been binded to a physical node and pin */
|
|
check_physical_pb_graph_node_annotation(vpr_device_ctx, const_cast<const VprDeviceAnnotation&>(vpr_device_annotation));
|
|
}
|
|
|
|
} /* end namespace openfpga */
|
|
|