AurelienUoU ba05a08ef0 Path correction in tech debugging + correction of yosys rewrite file in fpga_flow		2019-05-30 09:52:19 -06:00
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ARCH	Update spice path in architecture	2019-05-29 10:08:58 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	add num_driver_nodes to Switch Block XML writter	2019-05-28 20:52:33 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	Add travis full path to avoid missing sources	2019-05-16 15:51:10 -06:00
.regression_verilog.sh	Path correction in tech debugging + correction of yosys rewrite file in fpga_flow	2019-05-30 09:52:19 -06:00
CMakeLists.txt	Force graphics to false	2019-05-15 15:01:54 -06:00
Makefile	fixed bugs in CMakeLists.txt and Makefile	2019-05-03 23:03:04 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	correction Null issue for the flat model	2019-05-28 14:15:24 -06:00