283 lines
7.8 KiB
Verilog
283 lines
7.8 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Interface ////
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//// This is the external bus interface, that is WISHBONE ////
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//// SoC compliant. ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/usb/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2003 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: usbf_wb.v,v 1.4 2003/10/17 02:36:57 rudi Exp $
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//
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// $Date: 2003/10/17 02:36:57 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: usbf_wb.v,v $
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// Revision 1.4 2003/10/17 02:36:57 rudi
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// - Disabling bit stuffing and NRZI encoding during speed negotiation
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// - Now the core can send zero size packets
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// - Fixed register addresses for some of the higher endpoints
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// (conversion between decimal/hex was wrong)
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// - The core now does properly evaluate the function address to
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// determine if the packet was intended for it.
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// - Various other minor bugs and typos
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//
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// Revision 1.3 2001/09/24 01:15:28 rudi
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//
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// Changed reset to be active high async.
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//
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// Revision 1.2 2001/08/10 08:48:33 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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//
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// Revision 1.1 2001/08/03 05:30:09 rudi
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//
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//
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// 1) Reorganized directory structure
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//
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// Revision 1.2 2001/03/31 13:00:52 rudi
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//
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// - Added Core configuration
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// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode
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// - Modified WISHBONE interface and sync logic
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// - Moved SSRAM outside the core (added interface)
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// - Many small bug fixes ...
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//
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// Revision 1.0 2001/03/07 09:17:12 rudi
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//
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//
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// Changed all revisions to revision 1.0. This is because OpenCores CVS
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// interface could not handle the original '0.1' revision ....
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//
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// Revision 0.1.0.1 2001/02/28 08:11:47 rudi
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// Initial Release
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//
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//
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`include "usbf_defines.v"
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module usbf_wb( // WISHBONE Interface
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wb_clk, phy_clk, rst, wb_addr_i, wb_data_i, wb_data_o,
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wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i,
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// Memory Arbiter Interface
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ma_adr, ma_dout, ma_din, ma_we, ma_req, ma_ack,
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// Register File interface
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rf_re, rf_we, rf_din, rf_dout);
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input wb_clk, phy_clk;
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input rst;
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input [`USBF_UFC_HADR:0] wb_addr_i;
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input [31:0] wb_data_i;
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output [31:0] wb_data_o;
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output wb_ack_o;
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input wb_we_i;
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input wb_stb_i;
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input wb_cyc_i;
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// Memory Arbiter Interface
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output [`USBF_UFC_HADR:0] ma_adr;
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output [31:0] ma_dout;
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input [31:0] ma_din;
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output ma_we;
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output ma_req;
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input ma_ack;
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// Register File interface
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output rf_re;
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output rf_we;
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input [31:0] rf_din;
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output [31:0] rf_dout;
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///////////////////////////////////////////////////////////////////
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//
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// Local Wires and Registers
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//
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parameter [5:0] // synopsys enum state
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IDLE = 6'b00_0001,
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MA_WR = 6'b00_0010,
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MA_RD = 6'b00_0100,
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W0 = 6'b00_1000,
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W1 = 6'b01_0000,
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W2 = 6'b10_0000;
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reg [5:0] /* synopsys enum state */ state, next_state;
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// synopsys state_vector state
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reg wb_req_s1;
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reg wb_ack_d, wb_ack_s1, wb_ack_s1a, wb_ack_s2;
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reg ma_we;
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reg rf_re, rf_we_d;
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reg ma_req;
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reg wb_ack_o;
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reg [31:0] wb_data_o;
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///////////////////////////////////////////////////////////////////
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//
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// Interface Logic
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//
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assign ma_adr = wb_addr_i;
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assign ma_dout = wb_data_i;
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assign rf_dout = wb_data_i;
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always @(posedge wb_clk)
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if( `USBF_RF_SEL ) wb_data_o <= rf_din;
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else wb_data_o <= ma_din;
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// Sync WISHBONE Request
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always @(posedge phy_clk)
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wb_req_s1 <= wb_stb_i & wb_cyc_i;
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// Sync WISHBONE Ack
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always @(posedge wb_clk)
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wb_ack_s1 <= wb_ack_d;
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always @(posedge wb_clk)
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wb_ack_o <= wb_ack_s1 & !wb_ack_s2 & !wb_ack_o;
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always @(posedge wb_clk)
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wb_ack_s1a <= wb_ack_s1;
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always @(posedge wb_clk)
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wb_ack_s2 <= wb_ack_s1a;
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assign rf_we = rf_we_d;
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///////////////////////////////////////////////////////////////////
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//
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// Interface State Machine
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//
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`ifdef USBF_ASYNC_RESET
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always @(posedge phy_clk or negedge rst)
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`else
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always @(posedge phy_clk)
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`endif
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if(!rst) state <= IDLE;
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else state <= next_state;
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always @(state or wb_req_s1 or wb_addr_i or ma_ack or wb_we_i)
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begin
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next_state = state;
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ma_req = 1'b0;
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ma_we = 1'b0;
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wb_ack_d = 1'b0;
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rf_re = 1'b0;
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rf_we_d = 1'b0;
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case(state) // synopsys full_case parallel_case
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IDLE:
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begin
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if(wb_req_s1 && `USBF_MEM_SEL && wb_we_i)
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begin
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ma_req = 1'b1;
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ma_we = 1'b1;
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next_state = MA_WR;
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end
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if(wb_req_s1 && `USBF_MEM_SEL && !wb_we_i)
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begin
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ma_req = 1'b1;
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next_state = MA_RD;
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end
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if(wb_req_s1 && `USBF_RF_SEL && wb_we_i)
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begin
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rf_we_d = 1'b1;
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next_state = W0;
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end
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if(wb_req_s1 && `USBF_RF_SEL && !wb_we_i)
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begin
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rf_re = 1'b1;
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next_state = W0;
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end
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end
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MA_WR:
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begin
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if(!ma_ack)
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begin
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ma_req = 1'b1;
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ma_we = 1'b1;
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end
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else
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begin
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wb_ack_d = 1'b1;
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next_state = W1;
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end
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end
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MA_RD:
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begin
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if(!ma_ack)
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begin
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ma_req = 1'b1;
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end
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else
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begin
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wb_ack_d = 1'b1;
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next_state = W1;
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end
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end
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W0:
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begin
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wb_ack_d = 1'b1;
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next_state = W1;
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end
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W1:
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begin
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next_state = W2;
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end
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W2:
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begin
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next_state = IDLE;
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end
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endcase
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end
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endmodule
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