630 lines
28 KiB
C++
630 lines
28 KiB
C++
/*
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* Jason Luu 2008
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* Print complex block information to a file
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*/
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#include <cstdio>
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#include <cstdlib>
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#include <cstring>
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#include <vector>
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "vtr_digest.h"
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#include "vtr_memory.h"
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#include "vpr_types.h"
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#include "vpr_error.h"
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#include "pugixml.hpp"
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#include "globals.h"
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#include "atom_netlist.h"
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#include "pack_types.h"
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#include "cluster_router.h"
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#include "pb_type_graph.h"
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#include "output_clustering.h"
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#include "read_xml_arch_file.h"
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#include "vpr_utils.h"
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#define LINELENGTH 1024
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#define TAB_LENGTH 4
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/****************** Static variables local to this module ************************/
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static t_pb_graph_pin*** pb_graph_pin_lookup_from_index_by_type = nullptr; /* [0..device_ctx.logical_block_types.size()-1][0..num_pb_graph_pins-1] lookup pointer to pb_graph_pin from pb_graph_pin index */
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/**************** Subroutine definitions ************************************/
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/* Prints out one cluster (clb). Both the external pins and the *
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* internal connections are printed out. */
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static void print_stats() {
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int ipin;
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unsigned int itype;
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int total_nets_absorbed;
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std::unordered_map<AtomNetId, bool> nets_absorbed;
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int *num_clb_types, *num_clb_inputs_used, *num_clb_outputs_used;
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auto& device_ctx = g_vpr_ctx.device();
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auto& atom_ctx = g_vpr_ctx.atom();
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auto& cluster_ctx = g_vpr_ctx.clustering();
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num_clb_types = num_clb_inputs_used = num_clb_outputs_used = nullptr;
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num_clb_types = (int*)vtr::calloc(device_ctx.logical_block_types.size(), sizeof(int));
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num_clb_inputs_used = (int*)vtr::calloc(device_ctx.logical_block_types.size(), sizeof(int));
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num_clb_outputs_used = (int*)vtr::calloc(device_ctx.logical_block_types.size(), sizeof(int));
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for (auto net_id : atom_ctx.nlist.nets()) {
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nets_absorbed[net_id] = true;
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}
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/* Counters used only for statistics purposes. */
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for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
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auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
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auto physical_tile = pick_best_physical_type(logical_block);
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for (ipin = 0; ipin < logical_block->pb_type->num_pins; ipin++) {
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int physical_pin = get_physical_pin(physical_tile, logical_block, ipin);
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auto pin_class = physical_tile->pin_class[physical_pin];
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auto pin_class_inf = physical_tile->class_inf[pin_class];
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if (cluster_ctx.clb_nlist.block_pb(blk_id)->pb_route.empty()) {
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ClusterNetId clb_net_id = cluster_ctx.clb_nlist.block_net(blk_id, ipin);
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if (clb_net_id != ClusterNetId::INVALID()) {
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auto net_id = atom_ctx.lookup.atom_net(clb_net_id);
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VTR_ASSERT(net_id);
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nets_absorbed[net_id] = false;
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if (pin_class_inf.type == RECEIVER) {
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num_clb_inputs_used[logical_block->index]++;
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} else if (pin_class_inf.type == DRIVER) {
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num_clb_outputs_used[logical_block->index]++;
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}
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}
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} else {
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int pb_graph_pin_id = get_pb_graph_node_pin_from_block_pin(blk_id, ipin)->pin_count_in_cluster;
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const t_pb* pb = cluster_ctx.clb_nlist.block_pb(blk_id);
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if (pb->pb_route.count(pb_graph_pin_id)) {
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//Pin used
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auto atom_net_id = pb->pb_route[pb_graph_pin_id].atom_net_id;
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if (atom_net_id) {
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nets_absorbed[atom_net_id] = false;
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if (pin_class_inf.type == RECEIVER) {
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num_clb_inputs_used[logical_block->index]++;
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} else if (pin_class_inf.type == DRIVER) {
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num_clb_outputs_used[logical_block->index]++;
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}
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}
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}
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}
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}
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num_clb_types[logical_block->index]++;
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}
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for (itype = 0; itype < device_ctx.logical_block_types.size(); itype++) {
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if (num_clb_types[itype] == 0) {
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VTR_LOG("\t%s: # blocks: %d, average # input + clock pins used: %g, average # output pins used: %g\n",
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device_ctx.logical_block_types[itype].name, num_clb_types[itype], 0.0, 0.0);
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} else {
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VTR_LOG("\t%s: # blocks: %d, average # input + clock pins used: %g, average # output pins used: %g\n",
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device_ctx.logical_block_types[itype].name, num_clb_types[itype],
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(float)num_clb_inputs_used[itype] / (float)num_clb_types[itype],
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(float)num_clb_outputs_used[itype] / (float)num_clb_types[itype]);
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}
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}
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total_nets_absorbed = 0;
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for (auto net_id : atom_ctx.nlist.nets()) {
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if (nets_absorbed[net_id] == true) {
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total_nets_absorbed++;
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}
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}
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VTR_LOG("Absorbed logical nets %d out of %d nets, %d nets not absorbed.\n",
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total_nets_absorbed, (int)atom_ctx.nlist.nets().size(), (int)atom_ctx.nlist.nets().size() - total_nets_absorbed);
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free(num_clb_types);
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free(num_clb_inputs_used);
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free(num_clb_outputs_used);
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/* TODO: print more stats */
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}
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static const char* clustering_xml_net_text(AtomNetId net_id) {
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/* This routine prints out the atom_ctx.nlist net name (or open).
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* net_num is the index of the atom_ctx.nlist net to be printed
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*/
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if (!net_id) {
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return "open";
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} else {
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auto& atom_ctx = g_vpr_ctx.atom();
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return atom_ctx.nlist.net_name(net_id).c_str();
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}
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}
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static std::string clustering_xml_interconnect_text(t_logical_block_type_ptr type, int inode, const t_pb_routes& pb_route) {
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if (!pb_route.count(inode) || !pb_route[inode].atom_net_id) {
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return "open";
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}
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int prev_node = pb_route[inode].driver_pb_pin_id;
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int prev_edge;
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if (prev_node == OPEN) {
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/* No previous driver implies that this is either a top-level input pin or a primitive output pin */
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t_pb_graph_pin* cur_pin = pb_graph_pin_lookup_from_index_by_type[type->index][inode];
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VTR_ASSERT(cur_pin->parent_node->pb_type->parent_mode == nullptr || (cur_pin->is_primitive_pin() && cur_pin->port->type == OUT_PORT));
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return clustering_xml_net_text(pb_route[inode].atom_net_id);
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} else {
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t_pb_graph_pin* cur_pin = pb_graph_pin_lookup_from_index_by_type[type->index][inode];
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t_pb_graph_pin* prev_pin = pb_graph_pin_lookup_from_index_by_type[type->index][prev_node];
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for (prev_edge = 0; prev_edge < prev_pin->num_output_edges; prev_edge++) {
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VTR_ASSERT(prev_pin->output_edges[prev_edge]->num_output_pins == 1);
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if (prev_pin->output_edges[prev_edge]->output_pins[0]->pin_count_in_cluster == inode) {
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break;
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}
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}
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VTR_ASSERT(prev_edge < prev_pin->num_output_edges);
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char* name = prev_pin->output_edges[prev_edge]->interconnect->name;
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if (prev_pin->port->parent_pb_type->depth
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>= cur_pin->port->parent_pb_type->depth) {
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/* Connections from siblings or children should have an explicit index, connections from parent does not need an explicit index */
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return vtr::string_fmt("%s[%d].%s[%d]->%s",
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prev_pin->parent_node->pb_type->name,
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prev_pin->parent_node->placement_index,
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prev_pin->port->name,
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prev_pin->pin_number, name);
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} else {
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return vtr::string_fmt("%s.%s[%d]->%s",
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prev_pin->parent_node->pb_type->name,
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prev_pin->port->name,
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prev_pin->pin_number, name);
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}
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}
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}
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/* outputs a block that is open or unused.
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* In some cases, a block is unused for logic but is used for routing. When that happens, the block
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* cannot simply be marked open as that would lose the routing information. Instead, a block must be
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* output that reflects the routing resources used. This function handles both cases.
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*/
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static void clustering_xml_open_block(pugi::xml_node parent_node, t_logical_block_type_ptr type, t_pb_graph_node* pb_graph_node, int pb_index, bool is_used, const t_pb_routes& pb_route) {
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int i, j, k, m;
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const t_pb_type *pb_type, *child_pb_type;
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t_mode* mode = nullptr;
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int prev_node;
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int mode_of_edge, port_index, node_index;
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mode_of_edge = UNDEFINED;
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pb_type = pb_graph_node->pb_type;
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pugi::xml_node block_node = parent_node.append_child("block");
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block_node.append_attribute("name") = "open";
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block_node.append_attribute("instance") = vtr::string_fmt("%s[%d]", pb_graph_node->pb_type->name, pb_index).c_str();
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std::vector<std::string> block_modes;
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if (is_used) {
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/* Determine mode if applicable */
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port_index = 0;
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for (i = 0; i < pb_type->num_ports; i++) {
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if (pb_type->ports[i].type == OUT_PORT) {
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VTR_ASSERT(!pb_type->ports[i].is_clock);
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for (j = 0; j < pb_type->ports[i].num_pins; j++) {
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const t_pb_graph_pin* pin = &pb_graph_node->output_pins[port_index][j];
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node_index = pin->pin_count_in_cluster;
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if (pb_type->num_modes > 0 && pb_route.count(node_index) && pb_route[node_index].atom_net_id) {
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prev_node = pb_route[node_index].driver_pb_pin_id;
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const t_pb_graph_pin* prev_pin = pb_graph_pin_lookup_from_index_by_type[type->index][prev_node];
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const t_pb_graph_edge* edge = get_edge_between_pins(prev_pin, pin);
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VTR_ASSERT(edge != nullptr);
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mode_of_edge = edge->interconnect->parent_mode_index;
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if (mode != nullptr && &pb_type->modes[mode_of_edge] != mode) {
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VPR_FATAL_ERROR(VPR_ERROR_PACK,
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"Differing modes for block. Got %s previously and %s for edge %d (interconnect %s).",
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mode->name, pb_type->modes[mode_of_edge].name,
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port_index,
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edge->interconnect->name);
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}
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VTR_ASSERT(mode == nullptr || &pb_type->modes[mode_of_edge] == mode);
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mode = &pb_type->modes[mode_of_edge];
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}
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}
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port_index++;
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}
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}
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VTR_ASSERT(mode != nullptr && mode_of_edge != UNDEFINED);
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block_node.append_attribute("mode") = mode->name;
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block_node.append_attribute("pb_type_num_modes") = pb_type->num_modes;
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pugi::xml_node inputs_node = block_node.append_child("inputs");
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port_index = 0;
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for (i = 0; i < pb_type->num_ports; i++) {
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if (!pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT) {
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pugi::xml_node port_node = inputs_node.append_child("port");
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port_node.append_attribute("name") = pb_graph_node->pb_type->ports[i].name;
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std::vector<std::string> pins;
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for (j = 0; j < pb_type->ports[i].num_pins; j++) {
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node_index = pb_graph_node->input_pins[port_index][j].pin_count_in_cluster;
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if (pb_type->parent_mode == nullptr) {
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pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id));
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} else {
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pins.push_back(clustering_xml_interconnect_text(type, node_index, pb_route));
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}
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}
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port_node.text().set(vtr::join(pins.begin(), pins.end(), " ").c_str());
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port_index++;
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}
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}
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pugi::xml_node outputs_node = block_node.append_child("outputs");
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port_index = 0;
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for (i = 0; i < pb_type->num_ports; i++) {
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if (pb_type->ports[i].type == OUT_PORT) {
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VTR_ASSERT(!pb_type->ports[i].is_clock);
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pugi::xml_node port_node = outputs_node.append_child("port");
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port_node.append_attribute("name") = pb_graph_node->pb_type->ports[i].name;
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std::vector<std::string> pins;
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for (j = 0; j < pb_type->ports[i].num_pins; j++) {
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node_index = pb_graph_node->output_pins[port_index][j].pin_count_in_cluster;
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pins.push_back(clustering_xml_interconnect_text(type, node_index, pb_route));
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}
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port_node.text().set(vtr::join(pins.begin(), pins.end(), " ").c_str());
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port_index++;
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}
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}
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pugi::xml_node clock_node = block_node.append_child("clocks");
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port_index = 0;
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for (i = 0; i < pb_type->num_ports; i++) {
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if (pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT) {
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pugi::xml_node port_node = clock_node.append_child("port");
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port_node.append_attribute("name") = pb_graph_node->pb_type->ports[i].name;
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std::vector<std::string> pins;
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for (j = 0; j < pb_type->ports[i].num_pins; j++) {
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node_index = pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster;
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if (pb_type->parent_mode == nullptr) {
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pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id));
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} else {
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pins.push_back(clustering_xml_interconnect_text(type, node_index, pb_route));
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}
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}
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port_node.text().set(vtr::join(pins.begin(), pins.end(), " ").c_str());
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port_index++;
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}
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}
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if (pb_type->num_modes > 0) {
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for (i = 0; i < mode->num_pb_type_children; i++) {
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child_pb_type = &mode->pb_type_children[i];
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for (j = 0; j < mode->pb_type_children[i].num_pb; j++) {
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port_index = 0;
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is_used = false;
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for (k = 0; k < child_pb_type->num_ports && !is_used; k++) {
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if (child_pb_type->ports[k].type == OUT_PORT) {
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for (m = 0; m < child_pb_type->ports[k].num_pins; m++) {
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node_index = pb_graph_node->child_pb_graph_nodes[mode_of_edge][i][j].output_pins[port_index][m].pin_count_in_cluster;
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if (pb_route.count(node_index) && pb_route[node_index].atom_net_id) {
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is_used = true;
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break;
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}
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}
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port_index++;
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}
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}
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clustering_xml_open_block(block_node, type,
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&pb_graph_node->child_pb_graph_nodes[mode_of_edge][i][j],
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j, is_used, pb_route);
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}
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}
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}
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}
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}
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/* outputs a block that is used (i.e. has configuration) and all of its child blocks */
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static void clustering_xml_block(pugi::xml_node parent_node, t_logical_block_type_ptr type, t_pb* pb, int pb_index, const t_pb_routes& pb_route) {
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int i, j, k, m;
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const t_pb_type *pb_type, *child_pb_type;
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t_pb_graph_node* pb_graph_node;
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t_mode* mode;
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int port_index, node_index;
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bool is_used;
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pb_type = pb->pb_graph_node->pb_type;
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pb_graph_node = pb->pb_graph_node;
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mode = &pb_type->modes[pb->mode];
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pugi::xml_node block_node = parent_node.append_child("block");
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block_node.append_attribute("name") = pb->name;
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block_node.append_attribute("instance") = vtr::string_fmt("%s[%d]", pb_type->name, pb_index).c_str();
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if (pb_type->num_modes > 0) {
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block_node.append_attribute("mode") = mode->name;
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} else {
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const auto& atom_ctx = g_vpr_ctx.atom();
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AtomBlockId atom_blk = atom_ctx.nlist.find_block(pb->name);
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VTR_ASSERT(atom_blk);
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pugi::xml_node attrs_node = block_node.append_child("attributes");
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for (const auto& attr : atom_ctx.nlist.block_attrs(atom_blk)) {
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pugi::xml_node attr_node = attrs_node.append_child("attribute");
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attr_node.append_attribute("name") = attr.first.c_str();
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attr_node.text().set(attr.second.c_str());
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}
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pugi::xml_node params_node = block_node.append_child("parameters");
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for (const auto& param : atom_ctx.nlist.block_params(atom_blk)) {
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pugi::xml_node param_node = params_node.append_child("parameter");
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param_node.append_attribute("name") = param.first.c_str();
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param_node.text().set(param.second.c_str());
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}
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}
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pugi::xml_node inputs_node = block_node.append_child("inputs");
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port_index = 0;
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for (i = 0; i < pb_type->num_ports; i++) {
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if (!pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT) {
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pugi::xml_node port_node = inputs_node.append_child("port");
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port_node.append_attribute("name") = pb_graph_node->pb_type->ports[i].name;
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std::vector<std::string> pins;
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for (j = 0; j < pb_type->ports[i].num_pins; j++) {
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node_index = pb->pb_graph_node->input_pins[port_index][j].pin_count_in_cluster;
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if (pb_type->parent_mode == nullptr) {
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if (pb_route.count(node_index)) {
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pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id));
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} else {
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pins.push_back(clustering_xml_net_text(AtomNetId::INVALID()));
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}
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} else {
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pins.push_back(clustering_xml_interconnect_text(type, node_index, pb_route));
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}
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}
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port_node.text().set(vtr::join(pins.begin(), pins.end(), " ").c_str());
|
|
|
|
//The cluster router may have rotated equivalent pins (e.g. LUT inputs),
|
|
//record the resulting rotation here so it can be unambigously mapped
|
|
//back to the atom netlist
|
|
if (pb_type->ports[i].equivalent != PortEquivalence::NONE && pb_type->parent_mode != nullptr && pb_type->num_modes == 0) {
|
|
//This is a primitive with equivalent inputs
|
|
|
|
auto& atom_ctx = g_vpr_ctx.atom();
|
|
AtomBlockId atom_blk = atom_ctx.nlist.find_block(pb->name);
|
|
VTR_ASSERT(atom_blk);
|
|
|
|
AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, pb_type->ports[i].model_port);
|
|
|
|
if (atom_port) { //Port exists (some LUTs may have no input and hence no port in the atom netlist)
|
|
|
|
pugi::xml_node port_rotation_node = inputs_node.append_child("port_rotation_map");
|
|
port_rotation_node.append_attribute("name") = pb_graph_node->pb_type->ports[i].name;
|
|
|
|
std::set<AtomPinId> recorded_pins;
|
|
std::vector<std::string> pin_map_list;
|
|
|
|
for (j = 0; j < pb_type->ports[i].num_pins; j++) {
|
|
node_index = pb->pb_graph_node->input_pins[port_index][j].pin_count_in_cluster;
|
|
|
|
if (pb_route.count(node_index)) {
|
|
AtomNetId atom_net = pb_route[node_index].atom_net_id;
|
|
|
|
VTR_ASSERT(atom_net);
|
|
|
|
//This physical pin is in use, find the original pin in the atom netlist
|
|
AtomPinId orig_pin;
|
|
for (AtomPinId atom_pin : atom_ctx.nlist.port_pins(atom_port)) {
|
|
if (recorded_pins.count(atom_pin)) continue; //Don't add pins twice
|
|
|
|
AtomNetId atom_pin_net = atom_ctx.nlist.pin_net(atom_pin);
|
|
|
|
if (atom_pin_net == atom_net) {
|
|
recorded_pins.insert(atom_pin);
|
|
orig_pin = atom_pin;
|
|
break;
|
|
}
|
|
}
|
|
|
|
VTR_ASSERT(orig_pin);
|
|
//The physical pin j, maps to a pin in the atom netlist
|
|
pin_map_list.push_back(vtr::string_fmt("%d", atom_ctx.nlist.pin_port_bit(orig_pin)));
|
|
} else {
|
|
//The physical pin is disconnected
|
|
pin_map_list.push_back("open");
|
|
}
|
|
}
|
|
port_rotation_node.text().set(vtr::join(pin_map_list.begin(), pin_map_list.end(), " ").c_str());
|
|
}
|
|
}
|
|
|
|
port_index++;
|
|
}
|
|
}
|
|
|
|
pugi::xml_node outputs_node = block_node.append_child("outputs");
|
|
|
|
port_index = 0;
|
|
for (i = 0; i < pb_type->num_ports; i++) {
|
|
if (pb_type->ports[i].type == OUT_PORT) {
|
|
VTR_ASSERT(!pb_type->ports[i].is_clock);
|
|
|
|
pugi::xml_node port_node = outputs_node.append_child("port");
|
|
port_node.append_attribute("name") = pb_graph_node->pb_type->ports[i].name;
|
|
std::vector<std::string> pins;
|
|
for (j = 0; j < pb_type->ports[i].num_pins; j++) {
|
|
node_index = pb->pb_graph_node->output_pins[port_index][j].pin_count_in_cluster;
|
|
pins.push_back(clustering_xml_interconnect_text(type, node_index, pb_route));
|
|
}
|
|
port_node.text().set(vtr::join(pins.begin(), pins.end(), " ").c_str());
|
|
port_index++;
|
|
}
|
|
}
|
|
|
|
pugi::xml_node clock_node = block_node.append_child("clocks");
|
|
|
|
port_index = 0;
|
|
for (i = 0; i < pb_type->num_ports; i++) {
|
|
if (pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT) {
|
|
pugi::xml_node port_node = clock_node.append_child("port");
|
|
port_node.append_attribute("name") = pb_graph_node->pb_type->ports[i].name;
|
|
|
|
std::vector<std::string> pins;
|
|
for (j = 0; j < pb_type->ports[i].num_pins; j++) {
|
|
node_index = pb->pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster;
|
|
if (pb_type->parent_mode == nullptr) {
|
|
if (pb_route.count(node_index)) {
|
|
pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id));
|
|
} else {
|
|
pins.push_back(clustering_xml_net_text(AtomNetId::INVALID()));
|
|
}
|
|
} else {
|
|
pins.push_back(clustering_xml_interconnect_text(type, node_index, pb_route));
|
|
}
|
|
}
|
|
port_node.text().set(vtr::join(pins.begin(), pins.end(), " ").c_str());
|
|
port_index++;
|
|
}
|
|
}
|
|
|
|
if (pb_type->num_modes > 0) {
|
|
for (i = 0; i < mode->num_pb_type_children; i++) {
|
|
for (j = 0; j < mode->pb_type_children[i].num_pb; j++) {
|
|
/* If child pb is not used but routing is used, I must print things differently */
|
|
if ((pb->child_pbs[i] != nullptr) && (pb->child_pbs[i][j].name != nullptr)) {
|
|
clustering_xml_block(block_node, type, &pb->child_pbs[i][j], j, pb_route);
|
|
} else {
|
|
is_used = false;
|
|
child_pb_type = &mode->pb_type_children[i];
|
|
port_index = 0;
|
|
|
|
for (k = 0; k < child_pb_type->num_ports && !is_used; k++) {
|
|
if (child_pb_type->ports[k].type == OUT_PORT) {
|
|
for (m = 0; m < child_pb_type->ports[k].num_pins; m++) {
|
|
node_index = pb_graph_node->child_pb_graph_nodes[pb->mode][i][j].output_pins[port_index][m].pin_count_in_cluster;
|
|
if (pb_route.count(node_index) && pb_route[node_index].atom_net_id) {
|
|
is_used = true;
|
|
break;
|
|
}
|
|
}
|
|
port_index++;
|
|
}
|
|
}
|
|
clustering_xml_open_block(block_node, type,
|
|
&pb_graph_node->child_pb_graph_nodes[pb->mode][i][j],
|
|
j, is_used, pb_route);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* This routine dumps out the output netlist in a format suitable for *
|
|
* input to vpr. This routine also dumps out the internal structure of *
|
|
* the cluster, in essentially a graph based format. */
|
|
void output_clustering(const vtr::vector<ClusterBlockId, std::vector<t_intra_lb_net>*>& intra_lb_routing, bool global_clocks, const std::unordered_set<AtomNetId>& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering) {
|
|
auto& device_ctx = g_vpr_ctx.device();
|
|
auto& atom_ctx = g_vpr_ctx.atom();
|
|
auto& cluster_ctx = g_vpr_ctx.mutable_clustering();
|
|
|
|
if (!intra_lb_routing.empty()) {
|
|
VTR_ASSERT(intra_lb_routing.size() == cluster_ctx.clb_nlist.blocks().size());
|
|
for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
|
|
cluster_ctx.clb_nlist.block_pb(blk_id)->pb_route = alloc_and_load_pb_route(intra_lb_routing[blk_id], cluster_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node);
|
|
}
|
|
}
|
|
|
|
pb_graph_pin_lookup_from_index_by_type = new t_pb_graph_pin**[device_ctx.logical_block_types.size()];
|
|
for (unsigned int itype = 0; itype < device_ctx.logical_block_types.size(); itype++) {
|
|
pb_graph_pin_lookup_from_index_by_type[itype] = alloc_and_load_pb_graph_pin_lookup_from_index(&device_ctx.logical_block_types[itype]);
|
|
}
|
|
|
|
pugi::xml_document out_xml;
|
|
|
|
pugi::xml_node block_node = out_xml.append_child("block");
|
|
block_node.append_attribute("name") = out_fname;
|
|
block_node.append_attribute("instance") = "FPGA_packed_netlist[0]";
|
|
block_node.append_attribute("architecture_id") = architecture_id.c_str();
|
|
block_node.append_attribute("atom_netlist_id") = atom_ctx.nlist.netlist_id().c_str();
|
|
|
|
std::vector<std::string> inputs;
|
|
std::vector<std::string> outputs;
|
|
|
|
for (auto blk_id : atom_ctx.nlist.blocks()) {
|
|
auto type = atom_ctx.nlist.block_type(blk_id);
|
|
switch (type) {
|
|
case AtomBlockType::INPAD:
|
|
if (skip_clustering) {
|
|
VTR_ASSERT(0);
|
|
}
|
|
inputs.push_back(atom_ctx.nlist.block_name(blk_id));
|
|
break;
|
|
|
|
case AtomBlockType::OUTPAD:
|
|
if (skip_clustering) {
|
|
VTR_ASSERT(0);
|
|
}
|
|
outputs.push_back(atom_ctx.nlist.block_name(blk_id));
|
|
break;
|
|
|
|
case AtomBlockType::BLOCK:
|
|
if (skip_clustering) {
|
|
VTR_ASSERT(0);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
VTR_LOG_ERROR("in output_netlist: Unexpected type %d for atom block %s.\n",
|
|
type, atom_ctx.nlist.block_name(blk_id).c_str());
|
|
}
|
|
}
|
|
|
|
block_node.append_child("inputs").text().set(vtr::join(inputs.begin(), inputs.end(), " ").c_str());
|
|
block_node.append_child("outputs").text().set(vtr::join(outputs.begin(), outputs.end(), " ").c_str());
|
|
|
|
if (global_clocks) {
|
|
std::vector<std::string> clocks;
|
|
for (auto net_id : atom_ctx.nlist.nets()) {
|
|
if (is_clock.count(net_id)) {
|
|
clocks.push_back(atom_ctx.nlist.net_name(net_id));
|
|
}
|
|
}
|
|
|
|
block_node.append_child("clocks").text().set(vtr::join(clocks.begin(), clocks.end(), " ").c_str());
|
|
}
|
|
|
|
if (skip_clustering == false) {
|
|
for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
|
|
/* TODO: Must do check that total CLB pins match top-level pb pins, perhaps check this earlier? */
|
|
clustering_xml_block(block_node, cluster_ctx.clb_nlist.block_type(blk_id), cluster_ctx.clb_nlist.block_pb(blk_id), size_t(blk_id), cluster_ctx.clb_nlist.block_pb(blk_id)->pb_route);
|
|
}
|
|
}
|
|
|
|
out_xml.save_file(out_fname);
|
|
|
|
print_stats();
|
|
|
|
if (!intra_lb_routing.empty()) {
|
|
for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
|
|
cluster_ctx.clb_nlist.block_pb(blk_id)->pb_route.clear();
|
|
}
|
|
}
|
|
|
|
for (unsigned int itype = 0; itype < device_ctx.logical_block_types.size(); itype++) {
|
|
free_pb_graph_pin_lookup_from_index(pb_graph_pin_lookup_from_index_by_type[itype]);
|
|
}
|
|
delete[] pb_graph_pin_lookup_from_index_by_type;
|
|
}
|