112 lines
3.2 KiB
Perl
112 lines
3.2 KiB
Perl
#!usr/bin/perl -w
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use strict;
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#use Shell;
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use Time::gmtime;
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use Switch;
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use File::Path;
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use Cwd;
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my $mydate = gmctime();
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my $cwd = getcwd();
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sub gen_fpga_arch($ $)
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{
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my ($k,$n) = @_;
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my ($arch_file) = ("tmp.xml");
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my ($i) = int(0.5+$k*($n+1)/2);
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print "K=$k N=$n I=$i\n";
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my ($seq_out_up) = (2*$n-1);
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my %ble_h;
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my $ble_ptr = \%ble_h;
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my @comb;
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my @seq;
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my ($j);
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for ($j=0; $j<$k*$n; $j++) {
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my ($idx) = int($j/$k);
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print "idx=$idx";
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my ($input) = $j%$k;
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print " input=$input\n";
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$ble_ptr->{"ble_in$j"}->{ble_idx} = $idx;
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$ble_ptr->{"ble_in$j"}->{ble_input_idx} = $input;
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if ($input < $idx) {
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$ble_ptr->{"ble_in$j"}->{comb_in} = $input;
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}
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else {
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$ble_ptr->{"ble_in$j"}->{comb_in} = -1;
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}
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$ble_ptr->{"ble$idx"}->{"input$input"}->{idx} = $j;
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}
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my ($iseq,$icomb) = (0,0);
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for (my $ible=0; $ible<$n; $ible++) {
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for (my $in=0; $in<$ible; $in++) {
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if ($in < $ible) {
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$comb[$icomb] = $ble_ptr->{"ble$ible"}->{"input$in"}->{idx};
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$icomb++;
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}
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}
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for (my $in=$ible; $in<$k; $in++) {
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if ($in < $k) {
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$seq[$iseq] = $ble_ptr->{"ble$ible"}->{"input$in"}->{idx};
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$iseq++;
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}
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}
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}
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open (FARCH," > $arch_file") or die "Fail to create $arch_file";
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print FARCH "<pb_type name=\"clb\">\n";
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print FARCH " <input name=\"I\" num_pins=\"$i\" equivalent=\"true\"/>\n";
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print FARCH " <output name=\"O\" num_pins=\"$n\" equivalent=\"false\"/>\n";
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print FARCH " <clock name=\"clk\" num_pins=\"1\"/>\n";
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print FARCH " <interconnect>\n";
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print FARCH " <complete name=\"clks\" input=\"clb.clk\" output=\"ble.clk\"/>\n";
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print FARCH " <complete name=\"crossbar_in0\" input=\"clb.I ble.out[$seq_out_up:$n]\" output=\"";
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foreach my $tmp(@seq) {
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print FARCH "ble.in[$tmp] ";
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}
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print FARCH "\">\n";
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print FARCH " <delay_constant max=\"9.5e-11\" in_port=\"clb.I\" out_port=\"";
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foreach my $tmp(@seq) {
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print FARCH "ble.in[$tmp] ";
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}
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print FARCH "\"/>\n";
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print FARCH " <delay_constant max=\"7.5e-11\" in_port=\"ble.out[$seq_out_up:$n] \" out_port=\"";
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foreach my $tmp(@seq) {
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print FARCH "ble.in[$tmp] ";
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}
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print FARCH "\"/>\n";
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print FARCH "</complete>\n";
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my ($imux) = (0);
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foreach my $tmp(@comb) {
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print FARCH " <complete name=\"mux$imux\" input=\"clb.I ble.out[$seq_out_up:$n] ble.out[".$ble_ptr->{"ble_in$tmp"}->{comb_in}."]\" output=\"ble.in[$tmp]\">\n";
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print FARCH " <delay_constant max=\"9.5e-11\" in_port=\"clb.I\" out_port=\"ble.in[$tmp]\"/>\n";
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print FARCH " <delay_constant max=\"7.5e-11\" in_port=\"ble.out[$ble_ptr->{\"ble_in$tmp\"}->{comb_in}] \" out_port=\"ble.in[$tmp]\"/>\n";
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print FARCH " </complete>\n";
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$imux++;
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}
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for (my $i=0; $i<$n; $i++) {
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my $j = $i + $n;
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print FARCH " <mux name=\"mux$imux\" input=\"ble.out[$i] ble.out[$j]\" output=\"clb.O[$i]\">\n";
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print FARCH " <delay_constant max=\"9.5e-11\" in_port=\"ble.out[$i]\" out_port=\"clb.O[$i]\"/>\n";
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print FARCH " <delay_constant max=\"7.5e-11\" in_port=\"ble.out[$j]\" out_port=\"clb.O[$i]\"/>\n";
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print FARCH " </mux>\n";
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$imux++;
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}
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print FARCH " </interconnect>\n";
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}
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sub main()
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{
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my ($k,$n) = (6,7);
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&gen_fpga_arch($k,$n);
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}
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&main();
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