32 lines
1.5 KiB
C++
32 lines
1.5 KiB
C++
/******************************************************************************
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* This file introduces a data structure to store bitstream-related information
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******************************************************************************/
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#ifndef BITSTREAM_CONTEXT_H
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#define BITSTREAM_CONTEXT_H
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#include "vtr_vector.h"
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#include "bitstream_context_fwd.h"
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class BitstreamContext {
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private: /* Internal data */
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enum e_sram_orgz config_scheme_; /* The type of configuration protocol */
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CircuitModelId& sram_model_; /* The memory circuit model used by the Bitstream generation */
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size_t num_memory_bits_; /* Number of memory bits */
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size_t num_bls_; /* Number of Bit Lines */
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size_t num_wls_; /* Number of Word Lines */
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size_t num_reserved_bls_; /* Number of reserved Bit Lines, ONLY applicable to RRAM-based FPGA */
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size_t num_reserved_wls_; /* Number of reserved Word Lines, ONLY applicable to RRAM-based FPGA */
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/* Unique id of a bit in the Bitstream */
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vtr::vector<ConfigBitId, ConfigBitId> bit_ids_;
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/* Bit line address of a bit in the Bitream: ONLY applicable to memory-decoders */
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vtr::vector<ConfigBitId, size_t> bl_addr_;
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/* Word line address of a bit in the Bitream: ONLY applicable to memory-decoders */
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vtr::vector<ConfigBitId, size_t> wl_addr_;
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/* value of a bit in the Bitream */
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vtr::vector<ConfigBitId, bool> bit_val_;
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};
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#endif
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