24 lines
672 B
Verilog
24 lines
672 B
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Look-Up Tables
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// Author: Xifan TANG
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// Organization: EPFL/IC/LSI
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// Date: Thu Nov 15 14:26:04 2018
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//-----LUT module, verilog_model_name=lut4 -----
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module lut4 (input wire [0:3] in,
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output wire [0:0] out,
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input wire [0:15] sram_out,
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input wire [0:15] sram_outb
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);
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wire [0:3] in_b;
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assign in_b = ~ in;
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lut4_mux lut4_mux_0_ ( sram_out, out, in, in_b);
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endmodule
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//-----END LUT module, verilog_model_name=lut4 -----
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