176 lines
5.8 KiB
Verilog
176 lines
5.8 KiB
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Routing Channel - Y direction [1][1] in FPGA
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// Author: Xifan TANG
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// Organization: EPFL/IC/LSI
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// Date: Thu Nov 15 14:26:04 2018
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Verilog Module Channel Y [1][1] -----
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module chany_1__1_ (
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//----- BEGIN Global ports -----
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input [0:0] zin,
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input [0:0] clk,
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input [0:0] Reset,
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input [0:0] Set
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//----- END Global ports -----
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,
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input in0, //--- track 0 input
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output out1, //--- track 1 output
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input in2, //--- track 2 input
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output out3, //--- track 3 output
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input in4, //--- track 4 input
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output out5, //--- track 5 output
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input in6, //--- track 6 input
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output out7, //--- track 7 output
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input in8, //--- track 8 input
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output out9, //--- track 9 output
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input in10, //--- track 10 input
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output out11, //--- track 11 output
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input in12, //--- track 12 input
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output out13, //--- track 13 output
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input in14, //--- track 14 input
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output out15, //--- track 15 output
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input in16, //--- track 16 input
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output out17, //--- track 17 output
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input in18, //--- track 18 input
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output out19, //--- track 19 output
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input in20, //--- track 20 input
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output out21, //--- track 21 output
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input in22, //--- track 22 input
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output out23, //--- track 23 output
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input in24, //--- track 24 input
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output out25, //--- track 25 output
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input in26, //--- track 26 input
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output out27, //--- track 27 output
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input in28, //--- track 28 input
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output out29, //--- track 29 output
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output out0, //--- track 0 output
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input in1, //--- track 1 input
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output out2, //--- track 2 output
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input in3, //--- track 3 input
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output out4, //--- track 4 output
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input in5, //--- track 5 input
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output out6, //--- track 6 output
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input in7, //--- track 7 input
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output out8, //--- track 8 output
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input in9, //--- track 9 input
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output out10, //--- track 10 output
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input in11, //--- track 11 input
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output out12, //--- track 12 output
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input in13, //--- track 13 input
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output out14, //--- track 14 output
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input in15, //--- track 15 input
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output out16, //--- track 16 output
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input in17, //--- track 17 input
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output out18, //--- track 18 output
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input in19, //--- track 19 input
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output out20, //--- track 20 output
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input in21, //--- track 21 input
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output out22, //--- track 22 output
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input in23, //--- track 23 input
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output out24, //--- track 24 output
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input in25, //--- track 25 input
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output out26, //--- track 26 output
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input in27, //--- track 27 input
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output out28, //--- track 28 output
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input in29, //--- track 29 input
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output mid_out0, // Middle output 0 to logic blocks
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output mid_out1, // Middle output 1 to logic blocks
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output mid_out2, // Middle output 2 to logic blocks
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output mid_out3, // Middle output 3 to logic blocks
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output mid_out4, // Middle output 4 to logic blocks
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output mid_out5, // Middle output 5 to logic blocks
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output mid_out6, // Middle output 6 to logic blocks
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output mid_out7, // Middle output 7 to logic blocks
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output mid_out8, // Middle output 8 to logic blocks
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output mid_out9, // Middle output 9 to logic blocks
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output mid_out10, // Middle output 10 to logic blocks
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output mid_out11, // Middle output 11 to logic blocks
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output mid_out12, // Middle output 12 to logic blocks
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output mid_out13, // Middle output 13 to logic blocks
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output mid_out14, // Middle output 14 to logic blocks
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output mid_out15, // Middle output 15 to logic blocks
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output mid_out16, // Middle output 16 to logic blocks
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output mid_out17, // Middle output 17 to logic blocks
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output mid_out18, // Middle output 18 to logic blocks
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output mid_out19, // Middle output 19 to logic blocks
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output mid_out20, // Middle output 20 to logic blocks
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output mid_out21, // Middle output 21 to logic blocks
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output mid_out22, // Middle output 22 to logic blocks
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output mid_out23, // Middle output 23 to logic blocks
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output mid_out24, // Middle output 24 to logic blocks
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output mid_out25, // Middle output 25 to logic blocks
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output mid_out26, // Middle output 26 to logic blocks
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output mid_out27, // Middle output 27 to logic blocks
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output mid_out28, // Middle output 28 to logic blocks
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output mid_out29 // Middle output 29 to logic blocks
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);
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assign out0 = in0;
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assign mid_out0 = in0;
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assign out1 = in1;
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assign mid_out1 = in1;
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assign out2 = in2;
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assign mid_out2 = in2;
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assign out3 = in3;
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assign mid_out3 = in3;
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assign out4 = in4;
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assign mid_out4 = in4;
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assign out5 = in5;
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assign mid_out5 = in5;
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assign out6 = in6;
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assign mid_out6 = in6;
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assign out7 = in7;
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assign mid_out7 = in7;
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assign out8 = in8;
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assign mid_out8 = in8;
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assign out9 = in9;
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assign mid_out9 = in9;
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assign out10 = in10;
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assign mid_out10 = in10;
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assign out11 = in11;
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assign mid_out11 = in11;
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assign out12 = in12;
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assign mid_out12 = in12;
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assign out13 = in13;
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assign mid_out13 = in13;
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assign out14 = in14;
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assign mid_out14 = in14;
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assign out15 = in15;
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assign mid_out15 = in15;
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assign out16 = in16;
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assign mid_out16 = in16;
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assign out17 = in17;
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assign mid_out17 = in17;
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assign out18 = in18;
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assign mid_out18 = in18;
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assign out19 = in19;
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assign mid_out19 = in19;
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assign out20 = in20;
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assign mid_out20 = in20;
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assign out21 = in21;
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assign mid_out21 = in21;
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assign out22 = in22;
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assign mid_out22 = in22;
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assign out23 = in23;
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assign mid_out23 = in23;
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assign out24 = in24;
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assign mid_out24 = in24;
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assign out25 = in25;
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assign mid_out25 = in25;
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assign out26 = in26;
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assign mid_out26 = in26;
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assign out27 = in27;
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assign mid_out27 = in27;
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assign out28 = in28;
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assign mid_out28 = in28;
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assign out29 = in29;
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assign mid_out29 = in29;
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endmodule
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//----- END Verilog Module of Channel Y [1][1] -----
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