OpenFPGA/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_submodules.h

void dump_verilog_submodules(char* submodule_dir, 
                             t_arch Arch, 
                             t_det_routing_arch* routing_arch,
                             boolean include_timing,
							 boolean init_sim);