71 lines
2.8 KiB
C
71 lines
2.8 KiB
C
/***********************************/
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/* Synthesizable Verilog Dumping */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include "spice_types.h"
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#include "linkedlist.h"
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#include "fpga_spice_globals.h"
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#include "verilog_global.h"
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char* verilog_netlist_file_postfix = ".v";
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float verilog_sim_timescale = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns
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char* verilog_timing_preproc_flag = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
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char* verilog_init_sim_preproc_flag = "INITIALIZATION"; // the flag to enable initialization during simulation
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char* default_verilog_dir_name = "syn_verilogs/";
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char* default_lb_dir_name = "lb/";
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char* default_rr_dir_name = "routing/";
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char* default_submodule_dir_name = "sub_module/";
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char* default_modelsim_dir_name = "msim_projects/";
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char* modelsim_project_name_postfix = "_fpga_msim";
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char* modelsim_proc_script_name_postfix = "_proc.tcl";
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char* modelsim_top_script_name_postfix = "_runsim.tcl";
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char* modelsim_testbench_module_postfix = "_top_tb";
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char* modelsim_simulation_time_unit = "ms";
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char* verilog_top_postfix = "_top.v";
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char* bitstream_verilog_file_postfix = ".bitstream";
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char* top_testbench_verilog_file_postfix = "_top_tb.v";
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char* blif_testbench_verilog_file_postfix = "_blif_tb.v";
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char* submodule_verilog_file_name = "sub_module.v";
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char* logic_block_verilog_file_name = "logic_blocks.v";
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char* luts_verilog_file_name = "luts.v";
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char* routing_verilog_file_name = "routing.v";
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char* sub_module_verilog_file_name = "sub_module.v";
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char* muxes_verilog_file_name = "muxes.v";
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char* wires_verilog_file_name = "wires.v";
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char* essentials_verilog_file_name = "inv_buf_passgate.v";
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char* decoders_verilog_file_name = "decoders.v";
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char* verilog_mux_basis_posfix = "_basis";
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char* verilog_mux_special_basis_posfix = "_special_basis";
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/* Prefix for subckt Verilog netlists */
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char* grid_verilog_file_name_prefix = "grid_";
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char* chanx_verilog_file_name_prefix = "chanx_";
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char* chany_verilog_file_name_prefix = "chany_";
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char* sb_verilog_file_name_prefix = "sb_";
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char* cbx_verilog_file_name_prefix = "cbx_";
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char* cby_verilog_file_name_prefix = "cby_";
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/* SRAM SPICE MODEL should be set as global*/
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t_spice_model* sram_verilog_model = NULL;
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enum e_sram_orgz sram_verilog_orgz_type = SPICE_SRAM_STANDALONE;
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t_sram_orgz_info* sram_verilog_orgz_info = NULL;
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/* Input and Output Pad spice model. should be set as global */
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t_spice_model* iopad_verilog_model = NULL;
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/* Linked-list that stores all the configuration bits */
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t_llist* conf_bits_head = NULL;
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/* Linked-list that stores submodule Verilog file mames */
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t_llist* grid_verilog_subckt_file_path_head = NULL;
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t_llist* routing_verilog_subckt_file_path_head = NULL;
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t_llist* submodule_verilog_subckt_file_path_head = NULL;
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int verilog_default_signal_init_value = 0;
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