OpenFPGA/vpr7_x2p/vpr/SRC/fpga_spice/verilog
Aur??Lien ALACCHI eebdf7cb10 Add possibility to choose default value for initialization 2018-12-06 15:34:14 -07:00
..
verilog_api.c Correct sub_modules.v generation to include decoders.v when necessary 2018-12-05 13:52:25 -07:00
verilog_api.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_decoder.c Correct sub_modules.v generation to include decoders.v when necessary 2018-12-05 13:52:25 -07:00
verilog_decoder.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_global.c Add process for modelsim script autogeneration 2018-12-05 09:20:47 -07:00
verilog_global.h Add process for modelsim script autogeneration 2018-12-05 09:20:47 -07:00
verilog_lut.c fix bugs for wired LUTs 2018-11-27 12:46:30 -07:00
verilog_lut.h fix bugs for wired LUTs 2018-11-27 12:46:30 -07:00
verilog_modelsim_autodeck.c Edit auto-generated modelsim script 2018-12-05 16:15:29 -07:00
verilog_modelsim_autodeck.h Add forgottent files + add parameter transmission from verilog_api.c 2018-12-05 11:33:14 -07:00
verilog_pbtypes.c fix bugs for wired LUTs 2018-11-27 12:46:30 -07:00
verilog_pbtypes.h fix bugs for wired LUTs 2018-11-27 12:46:30 -07:00
verilog_primitives.c rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_primitives.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_routing.c rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_routing.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_submodules.c Add possibility to choose default value for initialization 2018-12-06 15:34:14 -07:00
verilog_submodules.h Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
verilog_top_netlist.c Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
verilog_top_netlist.h rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
verilog_utils.c Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
verilog_utils.h Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00