OpenFPGA/yosys/manual/PRESENTATION_ExAdv/select.ys

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read_verilog select.v
hierarchy -check -top test
proc; opt
cd test
select -set cone_a state_a %ci*:-$dff
select -set cone_b state_b %ci*:-$dff
select -set cone_ab @cone_a @cone_b %i
show -prefix select -format pdf -notitle \
-color red @cone_ab -color magenta @cone_a \
-color blue @cone_b