380 lines
14 KiB
C++
380 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <time.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static std::string id(std::string internal_id)
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{
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const char *str = internal_id.c_str();
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bool do_escape = false;
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if (*str == '\\')
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str++;
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if ('0' <= *str && *str <= '9')
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do_escape = true;
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for (int i = 0; str[i]; i++) {
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if ('0' <= str[i] && str[i] <= '9')
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continue;
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if ('a' <= str[i] && str[i] <= 'z')
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continue;
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if ('A' <= str[i] && str[i] <= 'Z')
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continue;
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if (str[i] == '_')
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continue;
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do_escape = true;
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break;
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}
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if (do_escape)
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return "\\" + std::string(str) + " ";
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return std::string(str);
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}
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static std::string idx(std::string str)
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{
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if (str[0] == '\\')
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return str.substr(1);
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return str;
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}
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static std::string idy(std::string str1, std::string str2 = std::string(), std::string str3 = std::string())
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{
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str1 = idx(str1);
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if (!str2.empty())
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str1 += "_" + idx(str2);
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if (!str3.empty())
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str1 += "_" + idx(str3);
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return id(str1);
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}
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static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int seed)
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{
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f << stringf("`ifndef outfile\n");
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f << stringf("\t`define outfile \"/dev/stdout\"\n");
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f << stringf("`endif\n");
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f << stringf("module testbench;\n\n");
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f << stringf("integer i;\n");
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f << stringf("integer file;\n\n");
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f << stringf("reg [31:0] xorshift128_x = 123456789;\n");
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f << stringf("reg [31:0] xorshift128_y = 362436069;\n");
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f << stringf("reg [31:0] xorshift128_z = 521288629;\n");
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f << stringf("reg [31:0] xorshift128_w = %u; // <-- seed value\n", seed ? seed : int(time(NULL)));
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f << stringf("reg [31:0] xorshift128_t;\n\n");
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f << stringf("task xorshift128;\n");
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f << stringf("begin\n");
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f << stringf("\txorshift128_t = xorshift128_x ^ (xorshift128_x << 11);\n");
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f << stringf("\txorshift128_x = xorshift128_y;\n");
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f << stringf("\txorshift128_y = xorshift128_z;\n");
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f << stringf("\txorshift128_z = xorshift128_w;\n");
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f << stringf("\txorshift128_w = xorshift128_w ^ (xorshift128_w >> 19) ^ xorshift128_t ^ (xorshift128_t >> 8);\n");
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it)
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{
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std::map<std::string, int> signal_in;
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std::map<std::string, std::string> signal_const;
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std::map<std::string, int> signal_clk;
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std::map<std::string, int> signal_out;
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RTLIL::Module *mod = it->second;
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if (mod->get_bool_attribute("\\gentb_skip"))
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continue;
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int count_ports = 0;
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log("Generating test bench for module `%s'.\n", it->first.c_str());
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for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); ++it2) {
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RTLIL::Wire *wire = it2->second;
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if (wire->port_output) {
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count_ports++;
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signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
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f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
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} else if (wire->port_input) {
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count_ports++;
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bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
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for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); ++it3)
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for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); ++it4) {
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if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
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continue;
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RTLIL::SigSpec &signal = (*it4)->signal;
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for (auto &c : signal.chunks())
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if (c.wire == wire)
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is_clksignal = true;
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}
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if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
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signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
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} else {
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signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
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if (wire->attributes.count("\\gentb_constant") != 0)
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signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string();
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}
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f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
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}
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}
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f << stringf("%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str());
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for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); ++it2) {
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RTLIL::Wire *wire = it2->second;
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if (wire->port_output || wire->port_input)
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f << stringf("\t.%s(%s)%s\n", id(wire->name.str()).c_str(),
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idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : "");
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}
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f << stringf(");\n\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "reset").c_str());
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f << stringf("begin\n");
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int delay_counter = 0;
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for (auto it = signal_in.begin(); it != signal_in.end(); ++it)
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f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
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for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it)
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f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
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f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
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for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) {
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f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
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f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
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}
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delay_counter = 0;
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for (auto it = signal_in.begin(); it != signal_in.end(); ++it)
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f << stringf("\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2);
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f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
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for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) {
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f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
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f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
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}
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delay_counter = 0;
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for (auto it = signal_in.begin(); it != signal_in.end(); ++it) {
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if (signal_const.count(it->first) == 0)
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continue;
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f << stringf("\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str());
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}
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f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "update_data").c_str());
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f << stringf("begin\n");
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delay_counter = 0;
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for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
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if (signal_const.count(it->first) > 0)
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continue;
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f << stringf("\txorshift128;\n");
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f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2);
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}
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f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "update_clock").c_str());
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f << stringf("begin\n");
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if (signal_clk.size()) {
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f << stringf("\txorshift128;\n");
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f << stringf("\t{");
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int total_clock_bits = 0;
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for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
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f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
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total_clock_bits += it->second;
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}
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f << stringf(" } = {");
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for (auto it = signal_clk.begin(); it != signal_clk.end(); it++)
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f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
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f << stringf(" } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits + 1);
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}
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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char shorthand = 'A';
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std::vector<std::string> header1;
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std::string header2 = "";
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f << stringf("task %s;\n", idy(mod->name.str(), "print_status").c_str());
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f << stringf("begin\n");
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f << stringf("\t$fdisplay(file, \"#OUT# %%b %%b %%b %%t %%d\", {");
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if (signal_in.size())
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for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
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f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str());
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int len = it->second;
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header2 += ", \"";
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if (len > 1)
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header2 += "/", len--;
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while (len > 1)
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header2 += "-", len--;
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if (len > 0)
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header2 += shorthand, len--;
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header2 += "\"";
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header1.push_back(" " + it->first);
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header1.back()[0] = shorthand;
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shorthand = shorthand == 'Z' ? 'A' : shorthand+1;
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}
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else {
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f << stringf(" 1'bx");
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header2 += ", \"#\"";
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}
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f << stringf(" }, {");
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header2 += ", \" \"";
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if (signal_clk.size()) {
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for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
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f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
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int len = it->second;
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header2 += ", \"";
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if (len > 1)
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header2 += "/", len--;
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while (len > 1)
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header2 += "-", len--;
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if (len > 0)
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header2 += shorthand, len--;
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header2 += "\"";
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header1.push_back(" " + it->first);
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header1.back()[0] = shorthand;
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shorthand = shorthand == 'Z' ? 'A' : shorthand+1;
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}
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} else {
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f << stringf(" 1'bx");
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header2 += ", \"#\"";
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}
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f << stringf(" }, {");
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header2 += ", \" \"";
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if (signal_out.size()) {
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for (auto it = signal_out.begin(); it != signal_out.end(); it++) {
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f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str());
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int len = it->second;
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header2 += ", \"";
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if (len > 1)
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header2 += "/", len--;
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while (len > 1)
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header2 += "-", len--;
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if (len > 0)
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header2 += shorthand, len--;
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header2 += "\"";
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header1.push_back(" " + it->first);
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header1.back()[0] = shorthand;
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shorthand = shorthand == 'Z' ? 'A' : shorthand+1;
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}
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} else {
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f << stringf(" 1'bx");
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header2 += ", \"#\"";
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}
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f << stringf(" }, $time, i);\n");
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "print_header").c_str());
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f << stringf("begin\n");
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f << stringf("\t$fdisplay(file, \"#OUT#\");\n");
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for (auto &hdr : header1)
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f << stringf("\t$fdisplay(file, \"#OUT# %s\");\n", hdr.c_str());
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f << stringf("\t$fdisplay(file, \"#OUT#\");\n");
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f << stringf("\t$fdisplay(file, {\"#OUT# \"%s});\n", header2.c_str());
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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f << stringf("task %s;\n", idy(mod->name.str(), "test").c_str());
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f << stringf("begin\n");
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f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str());
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f << stringf("\t%s;\n", idy(mod->name.str(), "reset").c_str());
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f << stringf("\tfor (i=0; i<%d; i=i+1) begin\n", num_iter);
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f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str());
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f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str());
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f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str());
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f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str());
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f << stringf("\tend\n");
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f << stringf("end\n");
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f << stringf("endtask\n\n");
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}
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f << stringf("initial begin\n");
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f << stringf("\t// $dumpfile(\"testbench.vcd\");\n");
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f << stringf("\t// $dumpvars(0, testbench);\n");
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f << stringf("\tfile = $fopen(`outfile);\n");
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for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it)
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if (!it->second->get_bool_attribute("\\gentb_skip"))
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f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str());
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f << stringf("\t$fclose(file);\n");
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f << stringf("\t$finish;\n");
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f << stringf("end\n\n");
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f << stringf("endmodule\n");
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}
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struct TestAutotbBackend : public Backend {
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TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" test_autotb [options] [filename]\n");
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log("\n");
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log("Automatically create primitive Verilog test benches for all modules in the\n");
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log("design. The generated testbenches toggle the input pins of the module in\n");
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log("a semi-random manner and dumps the resulting output signals.\n");
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log("\n");
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log("This can be used to check the synthesis results for simple circuits by\n");
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log("comparing the testbench output for the input files and the synthesis results.\n");
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log("\n");
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log("The backend automatically detects clock signals. Additionally a signal can\n");
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log("be forced to be interpreted as clock signal by setting the attribute\n");
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log("'gentb_clock' on the signal.\n");
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log("\n");
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log("The attribute 'gentb_constant' can be used to force a signal to a constant\n");
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log("value after initialization. This can e.g. be used to force a reset signal\n");
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log("low in order to explore more inner states in a state machine.\n");
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log("\n");
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log(" -n <int>\n");
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log(" number of iterations the test bench should run (default = 1000)\n");
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log("\n");
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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int num_iter = 1000;
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int seed = 0;
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log_header(design, "Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches).\n");
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int argidx;
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for (argidx = 1; argidx < GetSize(args); argidx++)
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{
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if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
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num_iter = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-seed" && argidx+1 < GetSize(args)) {
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seed = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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autotest(*f, design, num_iter, seed);
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}
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} TestAutotbBackend;
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PRIVATE_NAMESPACE_END
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