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| .. | ||
| basic_tests | ||
| benchmark_sweep | ||
| compilation_verification/config | ||
| fpga_bitstream | ||
| fpga_sdc/sdc_time_unit/config | ||
| fpga_spice/generate_spice/config | ||
| fpga_verilog | ||
| mcnc_big20/config | ||
| .gitignore | ||
| README.md | ||
README.md
Regression tests for OpenFPGA
The regression tests are grouped in category of OpenFPGA tools as well as integrated flows. The principle is that each OpenFPGA tool should have a set of regression tests.
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compilation_verfication: a quicktest after compilation
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Basic regression tests should focus on fundamental flow integration, such as
- Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run
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FPGA-Verilog regression tests should focus on testing fabric correctness, such as
- VPR + OpenFPGA integration for a BLIF-to-Verification flow-run
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FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites
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FPGA-SDC regression test should focus on SDC file generation and necessary syntax check
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FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.
Please keep this README up-to-date on the OpenFPGA tools