63 lines
1.3 KiB
Verilog
63 lines
1.3 KiB
Verilog
//-----------------------------------------------------
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// Design Name : dpram_2048x8
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// File Name : dpram_2048x8.v
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// Function : Dual port RAM 2048 x 8bit
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// Coder : Xifan Tang
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//-----------------------------------------------------
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module dpram_2048x8 (
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input clk,
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input wen,
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input ren,
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input[0:10] waddr,
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input[0:10] raddr,
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input[0:7] data_in,
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output[0:7] data_out );
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dual_port_sram memory_0 (
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.wclk (clk),
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.wen (wen),
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.waddr (waddr),
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.data_in (data_in),
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.rclk (clk),
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.ren (ren),
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.raddr (raddr),
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.data_out (data_out) );
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endmodule
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//-----------------------------------------------------
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// Design Name : dpram_2048x8_core
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// File Name : dpram_2048x8.v
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// Function : Core module of dual port RAM 2048 addresses x 8 bit
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// Coder : Xifan tang
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//-----------------------------------------------------
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module dual_port_sram (
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input wclk,
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input wen,
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input[0:10] waddr,
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input[0:7] data_in,
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input rclk,
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input ren,
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input[0:10] raddr,
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output[0:7] data_out );
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reg[0:7] ram[0:2047];
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reg[0:7] internal;
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assign data_out = internal;
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always @(posedge wclk) begin
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if(wen) begin
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ram[waddr] <= data_in;
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end
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end
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always @(posedge rclk) begin
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if(ren) begin
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internal <= ram[raddr];
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end
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end
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endmodule
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