296 lines
8.5 KiB
ReStructuredText
296 lines
8.5 KiB
ReStructuredText
.. _openfpga_setup_commands:
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Setup OpenFPGA
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--------------
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read_openfpga_arch
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~~~~~~~~~~~~~~~~~~
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Read the XML file about architecture description (see details in :ref:`arch_generality`)
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file openfpga_arch.xml``
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.. option:: --verbose
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Show verbose log
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write_openfpga_arch
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~~~~~~~~~~~~~~~~~~~
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Write the OpenFPGA XML architecture file to a file
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file arch_echo.xml``
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.. option:: --verbose
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Show verbose log
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read_openfpga_simulation_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Read the XML file about simulation settings (see details in :ref:`simulation_setting`)
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file auto_simulation_setting.xml``
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.. option:: --verbose
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Show verbose log
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write_openfpga_simulation_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Write the OpenFPGA XML simulation settings to a file
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file auto_simulation_setting_echo.xml``.
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See details about file format at :ref:`simulation_setting`.
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.. option:: --verbose
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Show verbose log
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read_openfpga_bitstream_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Read the XML file about bitstream settings (see details in :ref:`file_formats_bitstream_setting`)
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file bitstream_setting.xml``
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.. option:: --verbose
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Show verbose log
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write_openfpga_bitstream_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Write the OpenFPGA XML bitstream settings to a file
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.. option:: --file <string> or -f <string>
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Specify the file name. For example, ``--file auto_bitstream_setting_echo.xml``.
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See details about file format at :ref:`file_formats_bitstream_setting`.
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.. option:: --verbose
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Show verbose log
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link_openfpga_arch
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~~~~~~~~~~~~~~~~~~
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Annotate the OpenFPGA architecture to VPR data base
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.. option:: --activity_file <string>
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Specify the signal activity file. For example, ``--activity_file counter.act``.
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This is required when users wants OpenFPGA to automatically find the number of clocks in simulations. See details at :ref:`simulation_setting`.
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.. option:: --sort_gsb_chan_node_in_edges
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Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules
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.. option:: --verbose
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Show verbose log
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write_gsb_to_xml
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~~~~~~~~~~~~~~~~
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Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files
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.. option:: --file <string> or -f <string>
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Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file
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For example, ``--file /temp/gsb_output``
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.. option:: --unique
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Only output unique GSBs to XML files
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.. option:: --exclude_rr_info
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Exclude routing resource graph information from output files, e.g., node id as well as other attributes. This is useful to check the connection inside GSBs purely.
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.. option:: --exclude <string>
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Exclude part of the GSB data to be outputted. Can be [``sb``|``cbx``|``cby``]. Users can exclude multiple parts by using a splitter ``,``.
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For example,
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- ``--exclude sb``
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- ``--exclude [sb, cbx]``
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.. option:: --gsb_list <string>
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Specify the name of GSB to be outputted. Users can specify multiple GSBs by using a splitter ``,``.
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When specified, only the GSBs whose names match the list will be outputted to files.
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If not specified, all the GSBs will be outputted.
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For example,
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- ``--gsb_list [gsb_2__4_, gsb_3__2_]``
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- ``--gsb_list gsb_2__4_``
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.. option:: --verbose
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Show verbose log
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.. note:: This command is used to help users to study the difference between GSBs
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check_netlist_naming_conflict
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Check and correct any naming conflicts in the BLIF netlist
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This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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.. option:: --fix
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Apply fix-up to the names that violate the syntax
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.. option:: --report <string>
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Report the naming fix-up to an XML-based log file. For example, ``--report rename.xml``
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pb_pin_fixup
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~~~~~~~~~~~~
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Apply fix-up to clustering nets based on routing results
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This is strongly recommended. Otherwise, the bitstream generation may be wrong
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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.. option:: --verbose
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Show verbose log
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lut_truth_table_fixup
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~~~~~~~~~~~~~~~~~~~~~
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Apply fix-up to Look-Up Table truth tables based on packing results
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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.. option:: --verbose
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Show verbose log
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.. _cmd_build_fabric:
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build_fabric
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~~~~~~~~~~~~
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Build the module graph.
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.. option:: --compress_routing
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Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
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.. option:: --duplicate_grid_pin
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Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
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.. option:: --load_fabric_key <string>
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Load an external fabric key from an XML file. For example, ``--load_fabric_key fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
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.. option:: --generate_random_fabric_key
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Generate a fabric key in a random way
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.. option:: --write_fabric_key <string>.
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Output current fabric key to an XML file. For example, ``--write_fabric_key fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
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.. option:: --frame_view
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Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
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.. warning:: Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
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.. option:: --verbose
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Show verbose log
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.. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
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write_fabric_hierarchy
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~~~~~~~~~~~~~~~~~~~~~~
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Write the hierarchy of FPGA fabric graph to a plain-text file
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.. option:: --file <string> or -f <string>
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Specify the file name to write the hierarchy.
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.. option:: --depth <int>
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Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1.
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.. option:: --verbose
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Show verbose log
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.. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs).
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.. _openfpga_setup_commands_write_fabric_io_info:
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write_fabric_io_info
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~~~~~~~~~~~~~~~~~~~~
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Write the I/O information of FPGA fabric to an XML file
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.. option:: --file <string> or -f <string>
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Specify the file name to write the I/O information
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.. option:: --no_time_stamp
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Do not print time stamp in bitstream files
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.. option:: --verbose
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Show verbose log
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.. note:: This file is designed for pin constraint file conversion.
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pcf2place
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~~~~~~~~~
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Convert a Pin Constraint File (.pcf, see details in :ref:`file_format_pcf_file`) to a `placement file <https://docs.verilogtorouting.org/en/latest/vpr/file_formats/#placement-file-format-place>`_)
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.. option:: --pcf <string>
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Specify the path to the users' pin constraint file
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.. option:: --blif <string>
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Specify the path to the users' post-synthesis netlist
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.. option:: --fpga_io_map <string>
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Specify the path to the FPGA I/O location. Achieved by the command :ref:`openfpga_setup_commands_write_fabric_io_info`
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.. option:: --pin_table <string>
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Specify the path to the pin table file, which describes the pin mapping between chip I/Os and FPGA I/Os. See details in :ref:`file_format_pin_table_file`
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.. option:: --fpga_fix_pins <string>
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Specify the path to the placement file which will be outputted by running this command
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.. option:: --no_time_stamp
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Do not print time stamp in bitstream files
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.. option:: --verbose
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Show verbose log
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