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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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adb9162816
OpenFPGA
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openfpga_flow
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tasks
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quicklogic_tests
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sdc_controller_test
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Aram Kostanyan
6a4cc340a3
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00
..
config
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00