62 lines
1.1 KiB
Verilog
62 lines
1.1 KiB
Verilog
//-----------------------------------------------------
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// Design Name : dual_port_ram_tb
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// File Name : memory_wrapper_tb.v
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// Function : Dual port RAM 64x2048
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// Coder : Aurelien
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//-----------------------------------------------------
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`timescale 1 ns/1 ps
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module dpram_tb ();
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reg clk;
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reg wen;
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reg ren;
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reg[0:9] waddr;
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reg[0:9] raddr;
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reg[0:31] d_in;
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wire[0:31] d_out;
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integer count;
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integer lim_max = 1023;
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dpram memory_0 (
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.clk (clk),
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.wen (wen),
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.waddr (waddr),
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.d_in (d_in),
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.ren (ren),
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.raddr (raddr),
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.d_out (d_out) );
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initial begin
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clk <= 1'b0;
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ren <= 1'b0;
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wen <= 1'b0;
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raddr <= 10'h000;
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waddr <= 10'h000;
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d_in <= 32'h00000000;
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for(count = 0; count < lim_max; count = count +1) begin
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#5
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wen <= 1'b1;
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clk <= !clk;
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if(clk) begin
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waddr <= waddr + 1;
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end
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end
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wen <= 1'b0;
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for(count = 0; count < lim_max; count = count +1) begin
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#5
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ren <= 1'b1;
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clk <= !clk;
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if(clk) begin
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raddr <= raddr + 1;
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end
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end
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$finish;
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end
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always@(negedge clk) begin
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d_in <= $random;
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end
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endmodule
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