OpenFPGA/openfpga_flow/VerilogNetlists
tangxifan a308a13d7c use prefix instead of lib_name when building modules, then use lib_name for standard cell modules 2019-11-05 15:41:59 -07:00
..
adder.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
ff.v use prefix instead of lib_name when building modules, then use lib_name for standard cell modules 2019-11-05 15:41:59 -07:00
ff_tb.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
io.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
lb_tb.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
lut6.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
mux_tb.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
sram.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
sram_tb.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00