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aa070b2a41
OpenFPGA
/
yosys
/
manual
/
APPNOTE_011_Design_Investig...
/
cmos.v
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module
cmos_demo
(
input
a
,
b
,
output
[
1
:
0
]
y
)
;
assign
y
=
a
+
b
;
endmodule
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