tangxifan a8c803f08f try to fix bugs in explicit port mapping		2019-09-02 16:37:43 -06:00
..
base	try to fix bugs in explicit port mapping	2019-09-02 16:37:43 -06:00
bitstream	replace spice_models with circuit model in bitstream generator	2019-08-16 16:36:49 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
spice	added Switch Block SubType and SubFs for tileable rr_graph generation	2019-07-02 10:00:02 -06:00
verilog	debugged rram mux branch Verilog generation	2019-09-02 16:21:29 -06:00