tangxifan 49fa783914 [script] now suggest to skip pb_pin_fixup step in example scripts for most test cases		2022-09-29 10:45:27 -07:00
..
aib/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
embedded_io/config	[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases	2022-09-29 10:45:27 -07:00
multi_io_capacity/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
reduced_io/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
registerable_io/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
soc_io/config	[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases	2022-09-29 10:45:27 -07:00