123 lines
4.0 KiB
C++
123 lines
4.0 KiB
C++
/*********************************************************************
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* This file includes top-level function to generate SPICE primitive modules
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* and print them to files
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********************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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#include "spice_transistor_wrapper.h"
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#include "spice_essential_gates.h"
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#include "spice_mux.h"
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#include "spice_lut.h"
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#include "spice_memory.h"
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#include "spice_constants.h"
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#include "spice_submodule.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/*********************************************************************
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* Top-level function to generate primitive modules:
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* 1. Transistor wrapper
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* 2. Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
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* 3. Routing multiplexers
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* 4. TODO: Local encoders for routing multiplexers
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* 5. Wires
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* 6. Configuration memory blocks
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********************************************************************/
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int print_spice_submodule(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const Arch& openfpga_arch,
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const MuxLibrary& mux_lib,
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const std::string& submodule_dir) {
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int status = CMD_EXEC_SUCCESS;
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/* Transistor wrapper */
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status = print_spice_transistor_wrapper(netlist_manager,
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openfpga_arch.tech_lib,
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submodule_dir);
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/* Error out if fatal errors have been reported */
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if (CMD_EXEC_SUCCESS != status) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Constant modules: VDD and GND */
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status = print_spice_supply_wrappers(netlist_manager,
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module_manager,
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submodule_dir);
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/* Error out if fatal errors have been reported */
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if (CMD_EXEC_SUCCESS != status) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Logic gates:
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* - AND/OR,
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* - inverter, buffer
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* - transmission-gate/pass-transistor
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* - wires
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*/
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status = print_spice_essential_gates(netlist_manager,
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module_manager,
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openfpga_arch.circuit_lib,
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openfpga_arch.tech_lib,
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openfpga_arch.circuit_tech_binding,
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submodule_dir);
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/* Error out if fatal errors have been reported */
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if (CMD_EXEC_SUCCESS != status) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* TODO: local decoders for routing multiplexers */
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/* Routing multiplexers */
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status = print_spice_submodule_muxes(netlist_manager,
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module_manager,
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mux_lib,
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openfpga_arch.circuit_lib,
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submodule_dir);
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/* Error out if fatal errors have been reported */
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if (CMD_EXEC_SUCCESS != status) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Look-Up Tables */
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status = print_spice_submodule_luts(netlist_manager,
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module_manager,
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openfpga_arch.circuit_lib,
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submodule_dir);
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/* Error out if fatal errors have been reported */
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if (CMD_EXEC_SUCCESS != status) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Memories */
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status = print_spice_submodule_memories(netlist_manager,
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module_manager,
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mux_lib,
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openfpga_arch.circuit_lib,
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submodule_dir);
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/* Error out if fatal errors have been reported */
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if (CMD_EXEC_SUCCESS != status) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* TODO: architecture decoders */
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return status;
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}
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} /* end namespace openfpga */
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