54 lines
1.0 KiB
Verilog
54 lines
1.0 KiB
Verilog
//////////////////////////////////////
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// //
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// 2x2 Test-modes Low density //
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// //
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//////////////////////////////////////
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module test_mode_low (
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a,
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b,
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clk,
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out1,
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out2,
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out3,
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out4 );
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input wire a;
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input wire b;
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input wire clk;
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output wire out1,out2,out3,out4;
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reg[1:0] pipe_a;
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reg[1:0] pipe_b;
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reg[3:0] pipe_sum;
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wire[7:0] sum;
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assign sum[1:0] = pipe_a[1] + pipe_b[1] + pipe_sum[3];
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assign sum[3:2] = pipe_sum[0] + sum[1] + pipe_sum[2];
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assign sum[5:4] = pipe_sum[1] + sum[3] + pipe_sum[3];
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assign sum[7:6] = pipe_sum[2] + sum[5] + pipe_sum[0];
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assign out1 = pipe_sum[0];
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assign out2 = pipe_sum[1];
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assign out3 = pipe_sum[2];
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assign out4 = pipe_sum[3];
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initial begin
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pipe_a <= 2'b00;
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pipe_b <= 2'b00;
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pipe_sum <= 4'b0000;
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end
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always @(posedge clk) begin
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pipe_a[0] <= a;
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pipe_a[1] <= pipe_a[0];
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pipe_b[0] <= b;
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pipe_b[1] <= pipe_b[0];
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pipe_sum <= {sum[6], sum[4], sum[2], sum[0]};
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end
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endmodule
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