167 lines
6.2 KiB
Systemverilog
167 lines
6.2 KiB
Systemverilog
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`timescale 1ns/1ps
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`define assert_prog_clk( arg ) \
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assert property (@(posedge prog_clk) disable iff (pReset || (enable_assertions == 1'b0)) arg ) else $fatal("Simulation failed");
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`define assert_clk( arg ) \
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assert property (@(posedge clk) disable iff (Reset || ~Test_en || (enable_assertions == 1'b0)) arg ) else $fatal("Simulation failed");
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`define assert_undefined( arg ) \
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assert property (@(posedge clk) disable iff (pReset || Reset || (enable_assertions == 1'b0)) !$isunknown(arg)) else $fatal("Simulation failed");
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module inv_checker#(
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parameter enable_assertions = 1,
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BS_LGT = 8387,
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FF_n = 80
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)(
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//Top level inputs
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input [0:0] prog_clk,
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input [0:0] clk,
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input [0:0] pReset,
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input [0:0] Reset,
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input [0:0] Test_en,
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input [0:0] cc_spypad_0, // ok
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input [0:0] cc_spypad_1, // ok
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input [0:0] cc_spypad_2, // ok
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input [0:0] cout_spypad_0,
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input [0:0] lut4_out_0,
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input [0:0] lut4_out_1,
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input [0:0] lut4_out_2,
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input [0:0] lut4_out_3,
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input [0:0] lut5_out_0,
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input [0:0] lut5_out_1,
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input [0:0] lut6_out_0,
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input [0:0] perf_spypad_0,
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input [0:0] sc_spypad_0,
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input [0:0] shiftreg_spypad_0,
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// Inputs for CC PATH Check
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input [0:0] ccff_head,
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input [0:0] ccff_tail_gbot_1_0,
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input [0:0] ccff_head_gbot_2_0,
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input [0:0] ccff_head_gright_3_1,
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input [0:0] ccff_head_gright_3_2,
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input [0:0] ccff_tail_gright_3_2,
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input [0:0] ccff_head_sb_2_2,
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input [0:0] ccff_tail_sb_2_2,
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input [0:0] ccff_head_cbx_2_2,
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input [0:0] ccff_head_g11,
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input [0:0] ccff_head_g21,
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input [0:0] ccff_head_g22,
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input [0:0] ccff_head_g12,
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input [0:0] ccff_tail,
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// Inputs for SC PATH Check
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input [0:0] sc_head,
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input [0:0] sc_tail,
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input [0:0] sc_tail_clb_1_2,
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input [0:0] sc_tail_clb_1_1,
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input [0:0] sc_tail_clb_2_2,
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input [0:0] sc_tail_clb_2_1,
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// Ref signals for spypads
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input [0:0] cc_spypad_1_ref,
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input [0:0] cc_spypad_2_ref,
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input [0:0] cout_spypad_0_ref,
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input [0:0] lut4_out_0_ref,
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input [0:0] lut4_out_1_ref,
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input [0:0] lut4_out_2_ref,
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input [0:0] lut4_out_3_ref,
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input [0:0] lut5_out_0_ref,
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input [0:0] lut5_out_1_ref,
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input [0:0] lut6_out_0_ref,
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input [0:0] perf_spypad_0_ref,
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input [0:0] sc_spypad_0_ref,
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input [0:0] shiftreg_spypad_0_ref
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);
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bit reset_lock =0;
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bit preset_lock=0;
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reg [0:0] clk_sva = 1'b0;
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always
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begin
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#2.5 clk_sva[0] = ~clk_sva[0];
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end
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always @(posedge(Reset))
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begin
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reset_lock = 1'b1;
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end
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always @(posedge(pReset))
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begin
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preset_lock = 1'b1;
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end
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//No Signal should be undefined after Reset apart from gpio_pad
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U_prog_clk: `assert_undefined(prog_clk)
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U_clk: `assert_undefined(clk)
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U_pReset: `assert_undefined(pReset)
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U_Test_en: `assert_undefined(Test_en)
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U_ccff_head: `assert_undefined(ccff_head)
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// U_sc_head: `assert_undefined(sc_head) // This one depends on the test actually
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U_cc_spypad_0: `assert_undefined(cc_spypad_0)
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U_cc_spypad_1: `assert_undefined(cc_spypad_1)
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U_cc_spypad_2: `assert_undefined(cc_spypad_2)
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U_ccff_tail: `assert_undefined(ccff_tail)
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U_cout_spypad_0: `assert_undefined(cout_spypad_0)
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U_lut4_out_0: `assert_undefined(lut4_out_0)
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U_lut4_out_1: `assert_undefined(lut4_out_1)
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U_lut4_out_2: `assert_undefined(lut4_out_2)
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U_lut4_out_3: `assert_undefined(lut4_out_3)
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U_lut5_out_0: `assert_undefined(lut5_out_0)
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U_lut5_out_1: `assert_undefined(lut5_out_1)
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U_lut6_out_0: `assert_undefined(lut6_out_0)
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U_perf_spypad_0: `assert_undefined(perf_spypad_0)
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U_sc_spypad_0: `assert_undefined(sc_spypad_0)
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U_sc_tail: `assert_undefined(sc_tail)
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U_shiftreg_spypad_0: `assert_undefined(shiftreg_spypad_0)
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// Configuration chain path checker
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CC_TEST_HIGH: `assert_prog_clk( ccff_head |-> ##BS_LGT ccff_tail )
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CC_TEST_LOW: `assert_prog_clk( !ccff_head |-> ##BS_LGT !ccff_tail )
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Path1: `assert_prog_clk( ccff_tail_gbot_1_0 == ccff_head_gbot_2_0 )
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Path2: `assert_prog_clk( ccff_head_gright_3_1 |-> ##1 ccff_head_gright_3_2 )
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Path3: `assert_prog_clk( ccff_tail_gright_3_2 |-> ccff_head_sb_2_2 )
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Path4: `assert_prog_clk( ccff_head_sb_2_2 |-> ##(220) ccff_tail_sb_2_2 )
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Path5: `assert_prog_clk( ccff_tail_sb_2_2 == ccff_head_cbx_2_2 )
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Core_to_grid: `assert_prog_clk( ccff_head |-> ##1933 ccff_head_g11 )
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Grid1_1to2_1: `assert_prog_clk( ccff_head_g11 |-> ##1767 ccff_head_g21 )
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Grid2_1to2_2: `assert_prog_clk( ccff_head_g21 |-> ##1799 ccff_head_g22 )
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Grid2_2to1_2: `assert_prog_clk( ccff_head_g22 |-> ##1773 ccff_head_g12 )
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// Scan chain path checker
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SC_TEST: `assert_clk( sc_head |-> ##FF_n sc_tail)
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First_sc: `assert_clk( sc_head == sc_tail_clb_1_2)
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Second_sc: `assert_clk( sc_head |-> ##(FF_n/4) sc_tail_clb_1_1)
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Third_sc: `assert_clk( sc_head |-> ##(FF_n/2) sc_tail_clb_2_2)
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Fourth_sc: `assert_clk( sc_head |-> ##(3*FF_n/4) sc_tail_clb_2_1)
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// Spypad assertions
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ccff_head_top: `assert_prog_clk(ccff_head |-> ##1 cc_spypad_0)
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cc_spypad_1_check: `assert_prog_clk(cc_spypad_1_ref == cc_spypad_1)
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cc_spypad_2_check: `assert_prog_clk(cc_spypad_2_ref == cc_spypad_2)
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cout_spypad_0_check: `assert_clk(cout_spypad_0_ref == cout_spypad_0)
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lut4_out_0_check: `assert_clk(lut4_out_0_ref == lut4_out_0)
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lut4_out_1_check: `assert_clk(lut4_out_1_ref == lut4_out_1)
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lut4_out_2_check: `assert_clk(lut4_out_2_ref == lut4_out_2)
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lut4_out_3_check: `assert_clk(lut4_out_3_ref == lut4_out_3)
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lut5_out_0_check: `assert_clk(lut5_out_0_ref == lut5_out_0)
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lut5_out_1_check: `assert_clk(lut5_out_1_ref == lut5_out_1)
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lut6_out_0_check: `assert_clk(lut6_out_0_ref == lut6_out_0)
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perf_spypad_0_check: `assert_clk(perf_spypad_0_ref == perf_spypad_0)
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sc_spypad_0_check: `assert_clk(sc_spypad_0_ref == sc_spypad_0)
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shiftreg_spypad_0_check:`assert_prog_clk(shiftreg_spypad_0_ref == shiftreg_spypad_0)
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// Reset assertions
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reset_at_start: assert property
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(@(posedge clk_sva) disable iff (enable_assertions == 1'b0) ~reset_lock & ~Reset |-> ~clk)
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else $fatal("Reset has to trigger before stimuli goes in");
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preset_at_start: assert property
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(@(posedge clk_sva) disable iff (enable_assertions == 1'b0) ~preset_lock & ~pReset |-> ~prog_clk)
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else $fatal("pReset has to trigger before the beginning of programming phase");
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endmodule
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