65 lines
2.0 KiB
Verilog
65 lines
2.0 KiB
Verilog
/*
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* Copyright (C) 2020 The SymbiFlow Authors.
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*
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* Use of this source code is governed by a ISC-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/ISC
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*
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* SPDX-License-Identifier: ISC
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*/
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/*
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* Generated by harness_gen.py
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* From: VexRiscv.v
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*/
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module top(input wire clk, input wire stb, input wire di, output wire do);
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localparam integer DIN_N = 134;
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localparam integer DOUT_N = 148;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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VexRiscv dut(
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.externalResetVector(din[31:0]),
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.timerInterrupt(din[32]),
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.externalInterruptArray(din[64:33]),
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.iBusWishbone_CYC(dout[0]),
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.iBusWishbone_STB(dout[1]),
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.iBusWishbone_ACK(din[65]),
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.iBusWishbone_WE(dout[2]),
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.iBusWishbone_ADR(dout[32:3]),
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.iBusWishbone_DAT_MISO(din[97:66]),
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.iBusWishbone_DAT_MOSI(dout[64:33]),
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.iBusWishbone_SEL(dout[68:65]),
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.iBusWishbone_ERR(din[98]),
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.iBusWishbone_BTE(dout[70:69]),
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.iBusWishbone_CTI(dout[73:71]),
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.dBusWishbone_CYC(dout[74]),
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.dBusWishbone_STB(dout[75]),
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.dBusWishbone_ACK(din[99]),
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.dBusWishbone_WE(dout[76]),
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.dBusWishbone_ADR(dout[106:77]),
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.dBusWishbone_DAT_MISO(din[131:100]),
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.dBusWishbone_DAT_MOSI(dout[138:107]),
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.dBusWishbone_SEL(dout[142:139]),
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.dBusWishbone_ERR(din[132]),
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.dBusWishbone_BTE(dout[144:143]),
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.dBusWishbone_CTI(dout[147:145]),
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.clk(clk),
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.reset(din[133])
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);
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endmodule
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