24 lines
492 B
Verilog
24 lines
492 B
Verilog
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// Functionality: A FF with inverted clk. This is useful to test if an FPGA supports clock generation internally or an FPGA supports negative-edged clock
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// Author: Xifan Tang
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////////////////////////////////////////
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`timescale 1ns / 1ps
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module discrete_dffn(
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clk_ni,
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d_i,
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d_o);
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input wire clk_ni;
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input wire d_i;
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output reg d_o;
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wire int_clk;
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assign int_clk = ~clk_ni;
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always @(posedge int_clk) begin
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d_o <= d_i;
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end
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endmodule
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