29 lines
542 B
Verilog
29 lines
542 B
Verilog
/////////////////////////////////////////
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// Functionality: A two-stage clock divider (Frequency is divided by 4)
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// This is to test the clock generated locally by a LUT/FF
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// Author: Xifan Tang
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////////////////////////////////////////
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`timescale 1ns / 1ps
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module clk_divider(clk_i, clk_o);
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input wire clk_i;
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output reg clk_o;
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reg int_clk;
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initial begin
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clk_o <= 0;
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int_clk <= 0;
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end
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always @(posedge clk_i) begin
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int_clk <= ~int_clk;
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end
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always @(posedge int_clk) begin
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clk_o <= ~clk_o;
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end
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endmodule
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