158 lines
5.1 KiB
ReStructuredText
158 lines
5.1 KiB
ReStructuredText
.. _from_blif_to_verification:
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From BLIF to Verification
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-------------------------
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This tutorial will show an example how to
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- generate Verilog netlists for a FPGA fabric
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- generate Verilog testbenches for a RTL design
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- run HDL simulation to verify the functional correctness of the implemented FPGA fabric
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Netlist Generation
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~~~~~~~~~~~~~~~~~~
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We will use the openfpga_flow scripts (see details in :ref:`run_fpga_task`) to generate the Verilog netlists and testbenches.
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Here, we consider a representative but fairly simple FPGA architecture, which is based on 4-input LUTs.
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We will map a 2-input AND gate to the FPGA fabric, and run a full testbench (see details in :ref:`fpga_verilog_testbench`)
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We will simply execute the following openfpga task-run by
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.. code-block:: shell
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain
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Detailed settings, such as architecture XML files and RTL designs, can be found at ``${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf``.
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.. note:: ``${OPENFPGA_PATH}`` is the root directory of OpenFPGA
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After this task-run, you can find all the generated netlists and testbenches at
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.. code-block:: shell
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${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/
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.. note:: See :ref:`fabric_netlists` and :ref:`fpga_verilog_testbench` for the netlist details.
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Run icarus iVerilog Simulation
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Through OpenFPGA Scripts
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^^^^^^^^^^^^^^^^^^^^^^^^
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By default, the ``configuration_chain`` task-run will execute iVerilog simulation automatically.
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The simulation results are logged in
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.. code-block:: shell
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${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/vvp_sim_output.txt
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If the verification passed, you should be able to see ``Simulation Succeed`` in the log file.
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All the waveforms are stored in the ``and2_formal.vcd`` file.
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To visualize the waveforms, you can use the `GTKWave
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<http://gtkwave.sourceforge.net/>`_.
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.. code-block:: shell
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gtkwave ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
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Manual Method
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^^^^^^^^^^^^^
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If you want to run iVerilog simulation manually, you can follow these steps:
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.. code-block:: shell
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cd ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH
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source iverilog_output.txt
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vvp compiled_and2
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Debugging Tips
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^^^^^^^^^^^^^^
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If you want to apply full visibility to the signals, you need to change the following line in
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.. code-block:: shell
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${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_autocheck_top_tb.v
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from
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.. code-block:: shell
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$dumpvars (1, and2_autocheck_top_tb);
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to
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.. code-block:: shell
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$dumpvars (12, and2_autocheck_top_tb);
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Run Modelsim Simulation
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~~~~~~~~~~~~~~~~~~~~~~~
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Alternatively, you can run Modelsim simulations through openfpga_flow scripts or manually.
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Through OpenFPGA Scripts
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^^^^^^^^^^^^^^^^^^^^^^^^
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You can simply call the python script in the following line:
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.. code-block:: shell
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python3 openfpga_flow/scripts/run_modelsim.py openfpga_shell/full_testbench/configuration_chain --run_sim
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The script will automatically create a Modelsim project at
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.. code-block:: shell
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${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/MSIM2/
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and run the simulation.
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You may open the project and visualize the simulation results.
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Manual Method
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^^^^^^^^^^^^^
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Modify the ``fpga_defines.v`` (see details in :ref:`fabric_netlists`) at
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.. code-block:: shell
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${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shellfull_testbench//configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/
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by **deleting** the line
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.. code-block:: shell
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`define ICARUS_SIMULATOR 1
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Create a folder ``MSIM`` under
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.. code-block:: shell
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${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/
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Under the ``MSIM`` folder, create symbolic links to ``SRC`` folder and reference benchmarks by
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.. code-block:: shell
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ln -s ../SRC ./
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ln -s ../and2_output_verilog.v ./
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.. note:: Depending on the operating system, you may use other ways to create the symbolic links
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Launch ModelSim under the ``MSIM`` folder and create a project by following Modelsim user manuals.
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Add the following file to your project:
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.. code-block:: shell
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${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_include_netlists.v
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Compile the netlists, create a simulation configuration and specify ``and2_autocheck_top_tb`` at the top unit.
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Execute simulation with ``run -all``
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You should see ``Simulation Succeed`` in the output log.
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