30 lines
757 B
Verilog
30 lines
757 B
Verilog
//-----------------------------------------------------
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// Design Name : frac_mult_16x16
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// File Name : frac_mult_16x16.v
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// Function : A 16-bit multiplier which can operate in fracturable modes:
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// 1. two 8-bit multipliers
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// 2. one 16-bit multipliers
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// Coder : Xifan Tang
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//-----------------------------------------------------
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module frac_mult_16x16 (
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input [0:15] a,
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input [0:15] b,
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output [0:31] out,
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input [0:0] mode);
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reg [0:63] out_reg;
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always @(mode, a, b) begin
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if (1'b1 == mode) begin
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out_reg[0:15] <= a[0:7] * b[0:7];
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out_reg[16:31] <= a[8:15] * b[8:15];
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end else begin
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out_reg <= a * b;
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end
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end
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assign out = out_reg;
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endmodule
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