This website requires JavaScript.
Explore
Help
Sign In
riscv
/
OpenFPGA
mirror of
https://github.com/lnis-uofu/OpenFPGA.git
Watch
1
Star
0
Fork
You've already forked OpenFPGA
0
Code
Issues
Projects
Releases
Wiki
Activity
a2505ff16a
OpenFPGA
/
yosys
/
tests
/
lut
/
map_and.v
6 lines
77 B
Verilog
Raw
Blame
History
module
top
(
.
.
.
)
;
input
a
,
b
;
output
y
;
assign
y
=
a
&
b
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink