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a2505ff16a
OpenFPGA
/
yosys
/
manual
/
PRESENTATION_ExSyn
/
opt_01.v
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module
test
(
input
A
,
B
,
output
Y
)
;
assign
Y
=
A
?
A
?
B
:
1'b1
:
B
;
endmodule
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