This website requires JavaScript.
Explore
Help
Sign In
riscv
/
OpenFPGA
mirror of
https://github.com/lnis-uofu/OpenFPGA.git
Watch
1
Star
0
Fork
You've already forked OpenFPGA
0
Code
Issues
Projects
Releases
Wiki
Activity
a2505ff16a
OpenFPGA
/
yosys
/
manual
/
PRESENTATION_ExAdv
/
red_or3x1_cells.v
6 lines
95 B
Coq
Raw
Blame
History
module
OR3X1
(
A
,
B
,
C
,
Y
)
;
input
A
,
B
,
C
;
output
Y
;
assign
Y
=
A
|
B
|
C
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink