322 lines
14 KiB
C++
322 lines
14 KiB
C++
/********************************************************************
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* This file includes functions to print Verilog modules for a Grid
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* (CLBs, I/Os, heterogeneous blocks etc.)
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*******************************************************************/
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/* System header files */
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#include <vector>
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#include <fstream>
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/* Header files from external libs */
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#include "vtr_geometry.h"
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#include "util.h"
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#include "vtr_assert.h"
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#include "circuit_library_utils.h"
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/* Header files for VPR */
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#include "vpr_types.h"
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#include "globals.h"
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/* Header files for FPGA X2P tool suite */
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_types.h"
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_pbtypes_utils.h"
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#include "module_manager_utils.h"
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#include "fpga_x2p_globals.h"
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/* Header files for Verilog generator */
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#include "verilog_global.h"
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#include "verilog_utils.h"
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#include "verilog_writer_utils.h"
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#include "verilog_module_writer.h"
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#include "verilog_grid.h"
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/********************************************************************
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* Print Verilog modules of a primitive node in the pb_graph_node graph
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* This generic function can support all the different types of primitive nodes
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* i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders.
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*
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* The Verilog module will consist of two parts:
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* 1. Logic module of the primitive node
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* This module performs the logic function of the block
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* 2. Memory module of the primitive node
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* This module stores the configuration bits for the logic module
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* if the logic module is a programmable resource, such as LUT
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*
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* Verilog module structure:
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*
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* Primitive block
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* +---------------------------------------+
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* | |
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* | +---------+ +---------+ |
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* in |----->| |--->| |<------|configuration lines
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* | | Logic |... | Memory | |
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* out|<-----| |--->| | |
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* | +---------+ +---------+ |
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* | |
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* +---------------------------------------+
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*
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*******************************************************************/
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static
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void print_verilog_primitive_block(std::fstream& fp,
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ModuleManager& module_manager,
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t_pb_graph_node* primitive_pb_graph_node,
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const e_side& io_side,
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const bool& use_explicit_mapping) {
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/* Ensure a valid file handler */
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check_file_handler(fp);
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/* Ensure a valid pb_graph_node */
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if (NULL == primitive_pb_graph_node) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s,[LINE%d]) Invalid primitive_pb_graph_node!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Generate the module name for this primitive pb_graph_node*/
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std::string primitive_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side);
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std::string primitive_module_name = generate_physical_block_module_name(primitive_module_name_prefix, primitive_pb_graph_node->pb_type);
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/* Create a module of the primitive LUT and register it to module manager */
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ModuleId primitive_module = module_manager.find_module(primitive_module_name);
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/* Ensure that the module has been created and thus unique! */
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VTR_ASSERT(true == module_manager.valid_module_id(primitive_module));
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/* Write the verilog module */
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write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping);
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/* Add an empty line as a splitter */
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fp << std::endl;
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}
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/********************************************************************
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* Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.)
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* This function will traverse the graph of complex logic block (t_pb_graph_node)
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* in a recursive way, using a Depth First Search (DFS) algorithm.
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* As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph
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* will be printed out first, while the top-level will be printed out in the last
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*
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* Note: this function will print a unique Verilog module for each type of
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* t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly
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* hierarchical Verilog organization as well as simplify the Verilog file sizes.
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*
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* Note: DFS is the right way. Do NOT use BFS.
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* DFS can guarantee that all the sub-modules can be registered properly
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* to its parent in module manager
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*******************************************************************/
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static
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void print_verilog_physical_blocks_rec(std::fstream& fp,
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ModuleManager& module_manager,
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t_pb_graph_node* physical_pb_graph_node,
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const e_side& io_side,
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const bool& use_explicit_mapping) {
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/* Check the file handler*/
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check_file_handler(fp);
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/* Check cur_pb_graph_node*/
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if (NULL == physical_pb_graph_node) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Get the pb_type definition related to the node */
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t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
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/* Find the mode that physical implementation of a pb_type */
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int physical_mode_index = find_pb_type_physical_mode_index((*physical_pb_type));
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/* For non-leaf node in the pb_type graph:
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* Recursively Depth-First Generate all the child pb_type at the level
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*/
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if (FALSE == is_primitive_pb_type(physical_pb_type)) {
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for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) {
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/* Go recursive to visit the children */
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print_verilog_physical_blocks_rec(fp, module_manager,
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&(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]),
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io_side,
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use_explicit_mapping);
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}
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}
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/* For leaf node, a primitive Verilog module will be generated.
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* Note that the primitive may be mapped to a standard cell, we force to use that
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*/
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if (TRUE == is_primitive_pb_type(physical_pb_type)) {
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print_verilog_primitive_block(fp, module_manager,
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physical_pb_graph_node,
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io_side,
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true);
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/* Finish for primitive node, return */
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return;
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}
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/* Generate the name of the Verilog module for this pb_type */
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std::string pb_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side);
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std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type);
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/* Register the Verilog module in module manager */
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ModuleId pb_module = module_manager.find_module(pb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
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/* Comment lines */
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print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----"));
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/* Write the verilog module */
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write_verilog_module_to_file(fp, module_manager, pb_module, use_explicit_mapping);
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print_verilog_comment(fp, std::string("----- END Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----"));
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/* Add an empty line as a splitter */
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fp << std::endl;
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}
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/*****************************************************************************
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* This function will create a Verilog file and print out a Verilog netlist
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* for a type of physical block
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*
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* For IO blocks:
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* The param 'border_side' is required, which is specify which side of fabric
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* the I/O block locates at.
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*****************************************************************************/
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static
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void print_verilog_grid(ModuleManager& module_manager,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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t_type_ptr phy_block_type,
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const e_side& border_side,
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const bool& use_explicit_mapping) {
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/* Check code: if this is an IO block, the border side MUST be valid */
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if (IO_TYPE == phy_block_type) {
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VTR_ASSERT(NUM_SIDES != border_side);
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}
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/* Give a name to the Verilog netlist */
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/* Create the file name for Verilog */
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std::string verilog_fname(subckt_dir
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+ generate_grid_block_netlist_name(std::string(phy_block_type->name),
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IO_TYPE == phy_block_type,
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border_side,
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std::string(verilog_netlist_file_postfix))
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);
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/* TODO: remove the bak file when the file is ready */
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//verilog_fname += ".bak";
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/* Echo status */
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if (IO_TYPE == phy_block_type) {
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Side side_manager(border_side);
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vpr_printf(TIO_MESSAGE_INFO,
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"Writing FPGA Verilog Netlist (%s) for logic block %s at %s side ...\n",
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verilog_fname.c_str(), phy_block_type->name,
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side_manager.c_str());
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} else {
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vpr_printf(TIO_MESSAGE_INFO,
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"Writing FPGA Verilog Netlist (%s) for logic block %s...\n",
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verilog_fname.c_str(), phy_block_type->name);
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}
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_handler(fp);
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print_verilog_file_header(fp, std::string("Verilog modules for physical block: " + std::string(phy_block_type->name) + "]"));
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/* Print preprocessing flags */
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Print Verilog modules for all the pb_types/pb_graph_nodes
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* use a Depth-First Search Algorithm to print the sub-modules
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* Note: DFS is the right way. Do NOT use BFS.
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* DFS can guarantee that all the sub-modules can be registered properly
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* to its parent in module manager
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*/
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print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----"));
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/* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */
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print_verilog_physical_blocks_rec(fp, module_manager,
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phy_block_type->pb_graph_head,
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border_side,
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use_explicit_mapping);
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print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----"));
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/* Create a Verilog Module for the top-level physical block, and add to module manager */
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std::string grid_module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), std::string(phy_block_type->name), IO_TYPE == phy_block_type, border_side);
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ModuleId grid_module = module_manager.find_module(grid_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
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/* Write the verilog module */
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print_verilog_comment(fp, std::string("----- BEGIN Grid Verilog module: " + module_manager.module_name(grid_module) + " -----"));
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write_verilog_module_to_file(fp, module_manager, grid_module, use_explicit_mapping);
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print_verilog_comment(fp, std::string("----- END Grid Verilog module: " + module_manager.module_name(grid_module) + " -----"));
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/* Add an empty line as a splitter */
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fp << std::endl;
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/* Close file handler */
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fp.close();
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/* Add fname to the linked list */
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grid_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_verilog_subckt_file_path_head, verilog_fname.c_str());
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}
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/*****************************************************************************
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* Create logic block modules in a compact way:
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* 1. Only one module for each I/O on each border side (IO_TYPE)
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* 2. Only one module for each CLB (FILL_TYPE)
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* 3. Only one module for each heterogeneous block
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****************************************************************************/
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void print_verilog_grids(ModuleManager& module_manager,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const bool& use_explicit_mapping) {
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/* Enumerate the types, dump one Verilog module for each */
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for (int itype = 0; itype < num_types; itype++) {
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if (EMPTY_TYPE == &type_descriptors[itype]) {
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/* Bypass empty type or NULL */
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continue;
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} else if (IO_TYPE == &type_descriptors[itype]) {
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/* Special for I/O block, generate one module for each border side */
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for (int iside = 0; iside < NUM_SIDES; iside++) {
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Side side_manager(iside);
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print_verilog_grid(module_manager,
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verilog_dir, subckt_dir,
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&type_descriptors[itype],
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side_manager.get_side(),
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use_explicit_mapping);
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}
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continue;
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} else if (FILL_TYPE == &type_descriptors[itype]) {
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/* For CLB */
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print_verilog_grid(module_manager,
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verilog_dir, subckt_dir,
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&type_descriptors[itype],
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NUM_SIDES,
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use_explicit_mapping);
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continue;
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} else {
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/* For heterogenenous blocks */
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print_verilog_grid(module_manager,
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verilog_dir, subckt_dir,
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&type_descriptors[itype],
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NUM_SIDES,
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use_explicit_mapping);
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}
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}
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/* Output a header file for all the logic blocks */
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vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid Verilog modules...\n");
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std::string grid_verilog_fname(logic_block_verilog_file_name);
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/* TODO: remove .bak when it is ready */
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//grid_verilog_fname += ".bak";
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dump_verilog_subckt_header_file(grid_verilog_subckt_file_path_head,
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subckt_dir.c_str(),
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grid_verilog_fname.c_str());
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}
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