266 lines
11 KiB
C++
266 lines
11 KiB
C++
/**********************************************************
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* MIT License
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*
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* Copyright (c) 2018 LNIS - The University of Utah
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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***********************************************************************/
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/************************************************************************
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* Filename: circuit_library_utils.cpp
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* Created by: Xifan Tang
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* Change history:
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* +-------------------------------------+
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* | Date | Author | Notes
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* +-------------------------------------+
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* | 2019/09/27 | Xifan Tang | Created
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* +-------------------------------------+
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***********************************************************************/
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/************************************************************************
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* Function to perform fundamental operation for the circuit library
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* These functions are not universal methods for the CircuitLibrary class
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* They are made to ease the development in some specific purposes
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* Please classify such functions in this file
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***********************************************************************/
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/* Header files should be included in a sequence */
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/* Standard header files required go first */
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#include <algorithm>
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#include "vtr_assert.h"
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#include "util.h"
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#include "circuit_library_utils.h"
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/********************************************************************
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* Get the model id of a SRAM model that is used to configure
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* a circuit model
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*******************************************************************/
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std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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/* SRAM model id is stored in the sram ports of a circuit model */
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM);
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std::vector<CircuitModelId> sram_models;
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/* Create a list of sram models, but avoid duplicated model ids */
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for (const auto& sram_port : sram_ports) {
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CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
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VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
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if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) {
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continue; /* Already in the list, skip the addition */
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}
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/* Not in the list, add it */
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sram_models.push_back(sram_model);
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}
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return sram_models;
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}
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/********************************************************************
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* Find regular (not mode select) sram ports of a circuit model
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*******************************************************************/
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std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true);
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std::vector<CircuitPortId> regular_sram_ports;
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for (const auto& port : sram_ports) {
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if (true == circuit_lib.port_is_mode_select(port)) {
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continue;
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}
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regular_sram_ports.push_back(port);
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}
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return regular_sram_ports;
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}
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/********************************************************************
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* Find mode select sram ports of a circuit model
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*******************************************************************/
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std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true);
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std::vector<CircuitPortId> mode_select_sram_ports;
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for (const auto& port : sram_ports) {
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if (false == circuit_lib.port_is_mode_select(port)) {
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continue;
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}
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mode_select_sram_ports.push_back(port);
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}
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return mode_select_sram_ports;
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}
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/********************************************************************
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* Find the number of shared configuration bits for a ReRAM circuit
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* TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!!
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*******************************************************************/
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static
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size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
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const CircuitModelId& rram_model,
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const e_sram_orgz& sram_orgz_type) {
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size_t num_shared_config_bits = 0;
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/* Branch on the organization of configuration protocol */
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switch (sram_orgz_type) {
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case SPICE_SRAM_STANDALONE:
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case SPICE_SRAM_SCAN_CHAIN:
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break;
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case SPICE_SRAM_MEMORY_BANK: {
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/* Find BL/WL ports */
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std::vector<CircuitPortId> blb_ports = circuit_lib.model_ports_by_type(rram_model, SPICE_MODEL_PORT_BLB);
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for (auto blb_port : blb_ports) {
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num_shared_config_bits = std::max((int)num_shared_config_bits, (int)circuit_lib.port_size(blb_port) - 1);
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}
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break;
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}
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s,[LINE%d]) Invalid type of SRAM organization!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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return num_shared_config_bits;
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}
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/********************************************************************
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* A generic function to find the number of shared configuration bits
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* for circuit model
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* It will return 0 for CMOS circuits
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* It will return the maximum shared configuration bits across ReRAM models
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*
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* Note: This function may give WRONG results when all the SRAM ports
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* are not properly linked to its circuit models!
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* So, it should be called after the SRAM linking is done!!!
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*
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* IMPORTANT: This function should NOT be used to find the number of shared configuration bits
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* for a multiplexer, because the multiplexer size is determined during
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* the FPGA architecture generation (NOT during the XML parsing).
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*******************************************************************/
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size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const e_sram_orgz& sram_orgz_type) {
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size_t num_shared_config_bits = 0;
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM);
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for (auto sram_port : sram_ports) {
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CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
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VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
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/* Depend on the design technolgy of SRAM model, the number of configuration bits will be different */
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switch (circuit_lib.design_tech_type(sram_model)) {
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case SPICE_MODEL_DESIGN_CMOS:
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/* CMOS circuit do not need shared configuration bits */
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break;
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case SPICE_MODEL_DESIGN_RRAM:
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/* RRAM circuit do need shared configuration bits, but it is subjected to the largest one among different SRAM models */
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num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, sram_orgz_type));
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s,[LINE%d]) Invalid design technology for SRAM model!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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}
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return num_shared_config_bits;
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}
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/********************************************************************
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* A generic function to find the number of configuration bits
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* for circuit model
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* It will sum up the sizes of all the sram ports
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*
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* IMPORTANT: This function should NOT be used to find the number of configuration bits
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* for a multiplexer, because the multiplexer size is determined during
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* the FPGA architecture generation (NOT during the XML parsing).
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*******************************************************************/
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size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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size_t num_config_bits = 0;
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM);
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for (auto sram_port : sram_ports) {
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num_config_bits += circuit_lib.port_size(sram_port);
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}
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return num_config_bits;
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}
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/********************************************************************
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* A generic function to find all the global ports in a circuit library
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*
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* IMPORTANT: This function will uniquify the global ports whose share
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* share the same name !!!
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*******************************************************************/
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std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib) {
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std::vector<CircuitPortId> global_ports;
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for (auto port : circuit_lib.ports()) {
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/* By pass non-global ports*/
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if (false == circuit_lib.port_is_global(port)) {
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continue;
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}
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/* Check if a same port with the same name has already been in the list */
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bool add_to_list = true;
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for (const auto& global_port : global_ports) {
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if (0 == circuit_lib.port_prefix(port).compare(circuit_lib.port_prefix(global_port))) {
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/* Same name, skip list update */
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add_to_list = false;
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break;
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}
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}
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if (true == add_to_list) {
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/* Add the global_port to the list */
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global_ports.push_back(port);
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}
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}
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return global_ports;
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}
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/********************************************************************
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* A generic function to find all the unique user-defined
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* Verilog netlists in a circuit library
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* Netlists with same names will be considered as one
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*******************************************************************/
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std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib) {
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std::vector<std::string> netlists;
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for (const CircuitModelId& model : circuit_lib.models()) {
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/* Skip empty netlist names */
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if (true == circuit_lib.model_verilog_netlist(model).empty()) {
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continue;
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}
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/* See if the netlist name is already in the list */
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std::vector<std::string>::iterator it = std::find(netlists.begin(), netlists.end(), circuit_lib.model_verilog_netlist(model));
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if (it == netlists.end()) {
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netlists.push_back(circuit_lib.model_verilog_netlist(model));
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}
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}
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return netlists;
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}
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