325 lines
13 KiB
ReStructuredText
325 lines
13 KiB
ReStructuredText
Creating Spypads Using XML Syntax
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=================================
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Introduction
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~~~~~~~~~~~~
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**In this tutorial, we will**
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- Show the XML Syntax for Global Outputs
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- Showcase an example with Spypads
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- Modify an existing architecture to incorporate Spypads
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- Verify correctness through GTKWave
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Through this tutorial, we will show how to create Spypads in OpenFPGA.
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Spypads are physical output pins on a FPGA chip through which you can read out internal signals when doing silicon-level debugging. The XML syntax for spypads and other
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global signals can be found on our :ref:`circuit_library` documentation page.
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To create a spypad, the ``port type`` needs to be set to **output** and ``is_global`` and ``is_io`` need to be set to **true**:
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.. code-block:: xml
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<port type="output" is_global="true" is_io="true"/>
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When the port is syntactically correct, the outputs are independently wired from different instances to separated FPGA outputs and would physically look like :ref:`fig_gpout_ports`
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Pre-Built Spypads
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~~~~~~~~~~~~~~~~~
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An OpenFPGA architecture file that contains spypads and has a task that references it is the `k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml <https://github.com/lnis-uofu/OpenFPGA/blob/tutorials/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml>`_
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file. We can view ``k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml`` by entering the following command at the root directory of OpenFPGA:
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.. code-block:: bash
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emacs openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
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The spypads are defined from **LINE181** to **LINE183** and belong to the ``frac_lut6_spypad`` ``circuit_model`` that begins at **LINE172**
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.. code-block:: xml
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<circuit_model type="lut" name="frac_lut6_spypad" prefix="frac_lut6_spypad" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
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LINE181 <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3" is_global="true" is_io="true"/>
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LINE182 <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1" is_global="true" is_io="true"/>
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LINE183 <port type="output" prefix="lut6_out" size="1" lut_output_mask="0" is_global="true" is_io="true"/>
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<port type="sram" prefix="sram" size="64"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
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</circuit_model>
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The spypads are instantiated in the top-level verilog module ``fpga_top.v``. ``fpga_top.v`` is automatically generated when we run our task from the OpenFPGA root
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directory. However, we need to modify the task configuration file to run the **full testbench** instead of the **formal testbench** to view the spypads' waveforms in
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GTKWave.
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.. note:: To read about the differences between the **formal testbench** and the **full testbench**, please visit our page on testbenches: :ref:`testbench`.
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To open the task configuration file, run this command from the root directory of OpenFPGA:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf
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The last line of the task configuration file (**LINE44**) sets the **formal testbench** to be the desired testbench. To use the **full testbench**, comment out **LINE44**.
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The file will look like this when finished:
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.. code-block:: python
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:linenos:
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:emphasize-lines: 44
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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# Cannot pass automatically. Need change in .v file to match ports
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# When passed, we can replace the and2 benchmark
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#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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#bench0_top = test_mode_low
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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Our OpenFPGA task will now run the full testbench. We run the task with the following command from the root directory of OpenFPGA:
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.. code-block:: bash
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
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.. note:: Python 3.8 or later is required to run this task
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We can now see the instantiation of these spypads in ``fpga_top.v`` and ``luts.v``. We will start by viewing ``luts.v`` with the following command:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.verilog
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The spypads are coming from the ``frac_lut6_spypad`` circuit model. In ``luts.v``, the ``frac_lut6_spypad`` module is defined around **LINE150** and looks as follows:
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.. code-block:: verilog
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module frac_lut6_spypad(in,
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sram,
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sram_inv,
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mode,
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mode_inv,
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lut4_out,
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lut5_out,
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lut6_out);
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//----- INPUT PORTS -----
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input [0:5] in;
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//----- INPUT PORTS -----
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input [0:63] sram;
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//----- INPUT PORTS -----
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input [0:63] sram_inv;
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//----- INPUT PORTS -----
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input [0:1] mode;
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//----- INPUT PORTS -----
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input [0:1] mode_inv;
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//----- OUTPUT PORTS -----
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output [0:3] lut4_out;
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//----- OUTPUT PORTS -----
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output [0:1] lut5_out;
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//----- OUTPUT PORTS -----
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output [0:0] lut6_out;
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The ``fpga_top.v`` file has some similarities. We can view the ``fpga_top.v`` file by running the following command:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v
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If we look at the module definition and ports of ``fpga_top.v`` we should see the following:
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.. code-block:: verilog
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module fpga_top(pReset,
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prog_clk,
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TESTEN,
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set,
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reset,
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clk,
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gfpga_pad_frac_lut6_spypad_lut4_out,
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gfpga_pad_frac_lut6_spypad_lut5_out,
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gfpga_pad_frac_lut6_spypad_lut6_out,
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gfpga_pad_GPIO_PAD,
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ccff_head,
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ccff_tail);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- GLOBAL PORTS -----
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input [0:0] TESTEN;
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//----- GLOBAL PORTS -----
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input [0:0] set;
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//----- GLOBAL PORTS -----
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input [0:0] reset;
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//----- GLOBAL PORTS -----
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input [0:0] clk;
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//----- GPOUT PORTS -----
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output [0:3] gfpga_pad_frac_lut6_spypad_lut4_out;
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//----- GPOUT PORTS -----
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output [0:1] gfpga_pad_frac_lut6_spypad_lut5_out;
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//----- GPOUT PORTS -----
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output [0:0] gfpga_pad_frac_lut6_spypad_lut6_out;
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//----- GPIO PORTS -----
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inout [0:7] gfpga_pad_GPIO_PAD;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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Using :ref:`fig_gpout_ports` as a guide, we can relate our task like :numref:`fig_gpout_example`
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.. _fig_gpout:
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.. figure:: ./figures/gpout_ports_example.png
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:scale: 100%
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Diagram for ``lut6_out``
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We can view testbench waveforms with GTKWave by running the following command from the root directory:
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.. code-block:: bash
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gtkwave openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
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.. note::Information on GTKWave can be found on our documentation page located here: :ref:`verilog2verification`
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The waveforms will appear similar to :numref:`fig_spypad_waves`
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.. _fig_spypad_waves:
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.. figure:: ./figures/spypad_waveforms.png
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:scale: 100%
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Spypad Waveforms
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Building Spypads
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~~~~~~~~~~~~~~~~
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We will modify the `k6_frac_N10_adder_chain_40nm_openfpga.xml <https://github.com/lnis-uofu/OpenFPGA/blob/tutorials/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml>`_ file found in OpenFPGA to expose the **sumout** output from the **ADDF** module. We can start modifying
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the file by running the following command:
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.. code-block:: bash
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emacs openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
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Replace **LINE214** with the following:
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.. code-block:: xml
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<port type="output" prefix="sumout" lib_name="SUM" size="1" is_global=”true” is_io=”true”/>
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**sumout** is now a global output. **sumout** will show up in the ``fpga_top.v`` file and will have waveforms in GTKWave if we run the **full testbench**. To run the
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**full testbench**, we have to modify the ``hard_adder`` configuration file:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf
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Comment out the last line of the file to run the **full testbench**:
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.. code-block:: python
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#vpr_fpga_verilog_formal_verification_top_netlist=
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We now run the task to see our changes:
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.. code-block:: bash
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
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We can view the global ports in ``fpga_top.v`` by running the following command:
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.. code-block:: bash
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emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run064/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v
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The ``fpga_top.v`` should have the following in its module definition:
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.. code-block:: verilog
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module fpga_top(pReset,
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prog_clk,
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set,
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reset,
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clk,
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gfpga_pad_ADDF_sumout,
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gfpga_pad_GPIO_PAD,
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ccff_head,
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ccff_tail);
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- GLOBAL PORTS -----
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input [0:0] set;
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//----- GLOBAL PORTS -----
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input [0:0] reset;
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//----- GLOBAL PORTS -----
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input [0:0] clk;
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//----- GPOUT PORTS -----
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output [0:19] gfpga_pad_ADDF_sumout;
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We can view the waveform by running GTKWave:
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.. code-block:: bash
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gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
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The waveform should have some changes to its value. An example of what it may look like is displayed in :numref:`fig_spy_adder`
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.. _fig_spy_adder:
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.. figure:: ./figures/spyadder_waveform.png
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:scale: 100%
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Sumout Waveform
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Conclusion
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~~~~~~~~~~
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In this tutorial, we have shown how to build spypads into OpenFPGA Architectures using XML Syntax. If you have any issues, feel free to :ref:`contact` us.
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