This website requires JavaScript.
Explore
Help
Sign In
riscv
/
OpenFPGA
mirror of
https://github.com/lnis-uofu/OpenFPGA.git
Watch
1
Star
0
Fork
You've already forked OpenFPGA
0
Code
Issues
Projects
Releases
Wiki
Activity
a04555419a
OpenFPGA
/
yosys
/
tests
/
errors
/
syntax_err09.v
4 lines
42 B
Verilog
Raw
Blame
History
module
a
(
input
wire
x
=
1
'b0
)
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink