117 lines
5.3 KiB
ReStructuredText
117 lines
5.3 KiB
ReStructuredText
Link circuit modules
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--------------------
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Each defined SPICE model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-SPICE creating the SPICE netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
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SRAM
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====
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To link the defined circuit model of SRAM into the FPGA architecture description, a new line in XML format should be added under the XML node device. The new XML node is named as sram, which defines the area of an SRAM and the name of the circuit model to be linked. An example is shown as follows:
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.. code-block:: xml
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<sram area=”int” circuit_model_name=”string”>
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<sram>
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<spice organization="string" circuit_model_name="scff"/>
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<verilog organization="string" circuit_model_name="scff"/>
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</sram>
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* **area:** is expressed in terms of the number of minimum width transistors. The SRAM area defined in this line is used in the area estimation of global routing multiplexers. circuit_model_name should match the name of the circuit model that has been defined under XML node module_circuit_model. The type of the linked circuit model should be sram.
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* **organization:** [scan-chain|memory_bank|standalone], is the type of configuration circuits.
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:numref:`fig_sram` illustrates an example where a memory organization using memory decoders and 6-transistor SRAMs.
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.. _fig_sram:
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.. figure:: figures/sram.png
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:scale: 100%
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:alt: map to buried treasure
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Example of a memory organization using memory decoders
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.. note:: Currently SPICE only supports standalone memory organization.
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.. note:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
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Here is an example.
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.. code-block:: xml
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<sram area=”4” circuit_model_name=”sram6T”>
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Switch Boxes
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=============
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Original VPR architecture description contains an XML node called switchlist under which all the multiplexers of switch blocks are described.
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To link a defined SPICE model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions.
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Here is an example:
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.. code-block:: xml
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<switchlist>
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<switch type=”mux” name=”string” R=”float” Cin=”float” Cout=”float” Tdel=”float” mux_trans_size=”float” buf_size=”float” circuit_model_name=”string”/>
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</switchlist>
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* **circuit_model_name:** should match a circuit model whose type is mux defined under module_circuit_models.
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Connection Blocks
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================
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To link the defined SPICE model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
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Therefore, FPGA-SPICE requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined.
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Here is the example:
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.. code-block:: xml
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<cblock>
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<switch type=”mux” name=”string” R=”float” Cin=”float” Cout=”float” Tdel=”float” mux_trans_size=”float” buf_size=”float” circuit_model_name=”string”/>
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</cblock>
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* **circuit_model_name:** should match a circuit model whose type is mux defined under module_circuit_models.
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Channel Wire Segments
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=====================
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Similar to the Switch Boxes and Connection Blocks, the channel wire segments in the original architecture descriptions can be adapted to provide a link to the defined circuit model.
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.. code-block:: xml
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<segmentlist>
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<segment freq=”float” length=”int” type=”string” Rmetal=”float” Cmetal=”float” circuit_model_name=”string”/>
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</segmentlist>
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* circuit_model_name: should match a circuit model whose type is chan_wire defined under module_circuit_models.
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Primitive Blocks inside Configurable Logic Blocks
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=================================================
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The architecture description employs a hierarchy of pb_types to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model.
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.. code-block:: xml
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<pb_type name="clb" idle_mode_name="ble" physical_mode_name="ble">
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<pb_type name="ble">
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<pb_type name="lut" circuit_model_name="lut6">
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<pb_type name="ff" circuit_model_name="dff">
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<interconnect>
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<mux input="lut.out ff.Q" output="ble.out" circuit_model_name="mux_1level">
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</interconnect>
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</pb_type>
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<interconnect>
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<mux input="ble.out clb.in" output="ble.in" circuit_model_name="mux_2level">
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</interconnect>
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</pb_type>
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* **circuit_model_name:** should match a SPICE model defined under module_circuit_models. For the interconnection type direct, the type of the linked SPICE model should be wire. For mux, the type of linked SPICE model should be mux. For complete, the type of the linked SPICE model can be either mux or wire, depending on the case.
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* **idle_mode_name:** tell the name of the mode that the pb_type is configured to be by default. This is critical in building SPICE netlists for unused logic blocks.
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* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the block. This is critical in modeling actual circuit designs and architecture of an FPGA.
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