76 lines
1.9 KiB
Verilog
76 lines
1.9 KiB
Verilog
// Basic DFF
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module \$_DFF_P_ (D, C, Q);
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input D;
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input C;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
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endmodule
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// Async reset
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module \$_DFF_PP0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
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endmodule
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// Async active-low reset
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module \$_DFF_PN0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
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endmodule
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// Async reset, enable
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module \$_DFFE_PP0P_ (D, C, E, R, Q);
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input D;
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input C;
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input E;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
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endmodule
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// Latch with Async reset, enable
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module \$_DLATCH_PP0_ (input E, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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latchre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(R));
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endmodule
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// The following techmap operation are not performed right now
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// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
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// but in case we implement clock inversion in the future, the support is ready for it.
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module \$_DFF_N_ (D, CN, Q);
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input D;
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input CN;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN));
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endmodule
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module \$_DFF_NP0_ (D, CN, R, Q);
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input D;
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input CN;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN), .R(R));
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endmodule
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module \$_DFFE_NP0P_ (D, C, E, R, Q);
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input D;
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input C;
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input E;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
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endmodule
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