88 lines
1.6 KiB
Verilog
88 lines
1.6 KiB
Verilog
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// test_parser_constructs_module_basic1_test.v
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module f1_test;
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endmodule
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// test_parser_constructs_param_basic0_test.v
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module f2_test #( parameter v2kparam = 5)
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(in, out, io, vin, vout, vio);
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input in;
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output out;
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inout io;
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input [3:0] vin;
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output [v2kparam:0] vout;
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inout [0:3] vio;
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parameter myparam = 10;
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endmodule
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// test_parser_constructs_port_basic0_test.v
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module f3_test(in, out, io, vin, vout, vio);
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input in;
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output out;
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inout io;
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input [3:0] vin;
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output [3:0] vout;
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inout [0:3] vio;
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endmodule
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// test_parser_directives_define_simpledef_test.v
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`define parvez ahmad
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`define WIRE wire
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`define TEN 10
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module f4_`parvez();
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parameter param = `TEN;
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`WIRE w;
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assign w = `TEN;
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endmodule
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// test_parser_misc_operators_test.v
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module f5_test(out, i0, i1, i2, i3, s1, s0);
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output out;
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input i0, i1, i2, i3;
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input s1, s0;
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assign out = (~s1 & s0 & i0) |
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(~s1 & s0 & i1) |
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(s1 & ~s0 & i2) |
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(s1 & s0 & i3);
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endmodule
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module f5_ternaryop(out, i0, i1, i2, i3, s1, s0);
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output out;
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input i0, i1, i2, i3;
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input s1, s0;
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assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);
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endmodule
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module f5_fulladd4(sum, c_out, a, b, c_in);
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output [3:0] sum;
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output c_out;
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input [3:0] a, b;
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input c_in;
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assign {c_out, sum} = a + b + c_in;
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endmodule
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// test_parser_v2k_comb_port_data_type_test.v
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module f6_adder(sum , co, a, b, ci);
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output reg [31:0] sum;
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output reg co;
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input wire [31:0] a, b;
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input wire ci;
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endmodule
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// test_parser_v2k_comma_sep_sens_list_test.v
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module f7_test(q, d, clk, reset);
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output reg q;
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input d, clk, reset;
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always @ (posedge clk, negedge reset)
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if(!reset) q <= 0;
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else q <= d;
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endmodule
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