73 lines
2.7 KiB
C++
73 lines
2.7 KiB
C++
#ifndef OPENFPGA_REPACK_TEMPLATE_H
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#define OPENFPGA_REPACK_TEMPLATE_H
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/********************************************************************
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* This file includes functions to compress the hierachy of routing architecture
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*******************************************************************/
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#include "build_physical_truth_table.h"
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#include "command.h"
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#include "command_context.h"
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#include "command_exit_codes.h"
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#include "globals.h"
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#include "read_xml_repack_design_constraints.h"
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#include "repack.h"
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#include "repack_design_constraints.h"
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#include "vtr_log.h"
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#include "vtr_time.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* A wrapper function to call the fabric_verilog function of FPGA-Verilog
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*******************************************************************/
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template <class T>
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int repack_template(T& openfpga_ctx, const Command& cmd,
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const CommandContext& cmd_context) {
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CommandOptionId opt_design_constraints = cmd.option("design_constraints");
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CommandOptionId opt_ignore_global_nets =
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cmd.option("ignore_global_nets_on_pins");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* Load design constraints from file */
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RepackDesignConstraints repack_design_constraints;
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if (true == cmd_context.option_enable(cmd, opt_design_constraints)) {
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std::string dc_fname =
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cmd_context.option_value(cmd, opt_design_constraints);
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VTR_ASSERT(false == dc_fname.empty());
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repack_design_constraints =
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read_xml_repack_design_constraints(dc_fname.c_str());
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}
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/* Setup repacker options */
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RepackOption options;
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options.set_design_constraints(repack_design_constraints);
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options.set_ignore_global_nets_on_pins(
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cmd_context.option_value(cmd, opt_ignore_global_nets));
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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if (!options.valid()) {
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VTR_LOG("Detected errors when parsing options!\n");
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return CMD_EXEC_FATAL_ERROR;
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}
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pack_physical_pbs(g_vpr_ctx.device(), g_vpr_ctx.atom(),
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g_vpr_ctx.clustering(),
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openfpga_ctx.mutable_vpr_device_annotation(),
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openfpga_ctx.mutable_vpr_clustering_annotation(),
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openfpga_ctx.vpr_bitstream_annotation(),
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openfpga_ctx.arch().circuit_lib, options);
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build_physical_lut_truth_tables(
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openfpga_ctx.mutable_vpr_clustering_annotation(), g_vpr_ctx.atom(),
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g_vpr_ctx.clustering(), openfpga_ctx.vpr_device_annotation(),
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openfpga_ctx.arch().circuit_lib, options.verbose_output());
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/* TODO: should identify the error code from internal function execution */
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return CMD_EXEC_SUCCESS;
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}
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} /* end namespace openfpga */
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#endif
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