85 lines
2.6 KiB
Verilog
85 lines
2.6 KiB
Verilog
/* Generated by Yosys 0.9 (git sha1 f110c953, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */
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module counter(clk_counter, rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] , \q_counter[6] , \q_counter[7] );
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wire _00_;
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wire _01_;
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input clk_counter;
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wire n22;
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wire n26;
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wire n30;
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wire n34;
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wire n38;
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wire n42;
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wire n46;
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wire n50;
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output \q_counter[0] ;
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reg \q_counter[0] ;
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output \q_counter[1] ;
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reg \q_counter[1] ;
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output \q_counter[2] ;
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reg \q_counter[2] ;
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output \q_counter[3] ;
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reg \q_counter[3] ;
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output \q_counter[4] ;
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reg \q_counter[4] ;
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output \q_counter[5] ;
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reg \q_counter[5] ;
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output \q_counter[6] ;
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reg \q_counter[6] ;
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output \q_counter[7] ;
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reg \q_counter[7] ;
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input rst_counter;
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[0] <= 1'b0;
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else \q_counter[0] <= n22;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[1] <= 1'b0;
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else \q_counter[1] <= n26;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[2] <= 1'b0;
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else \q_counter[2] <= n30;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[3] <= 1'b0;
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else \q_counter[3] <= n34;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[4] <= 1'b0;
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else \q_counter[4] <= n38;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[5] <= 1'b0;
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else \q_counter[5] <= n42;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[6] <= 1'b0;
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else \q_counter[6] <= n46;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[7] <= 1'b0;
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else \q_counter[7] <= n50;
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end
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assign n26 = 8'h14 >> { \q_counter[0] , \q_counter[1] , rst_counter };
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assign n30 = 16'h0708 >> { \q_counter[2] , rst_counter, \q_counter[0] , \q_counter[1] };
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assign n34 = 32'd8323200 >> { \q_counter[3] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] };
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assign n38 = 64'h00007fff00008000 >> { \q_counter[4] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] };
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assign n42 = 8'h14 >> { _00_, \q_counter[5] , rst_counter };
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assign _00_ = 32'd2147483648 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] };
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assign n46 = 8'h14 >> { _01_, \q_counter[6] , rst_counter };
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assign _01_ = 64'h8000000000000000 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] };
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assign n50 = 16'h0708 >> { \q_counter[7] , rst_counter, _01_, \q_counter[6] };
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assign n22 = 4'h1 >> { \q_counter[0] , rst_counter };
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endmodule
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