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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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9adf94bfd3
OpenFPGA
/
openfpga_flow
/
tasks
/
quicklogic_tests
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lut_adder_test
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config
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tangxifan
e61857aa2b
Merge branch 'master' into ganesh_dev
2021-03-11 19:17:02 -07:00
..
bitstream_annotation.xml
[Test] Update bitstream annotation with new syntax
2021-03-10 20:45:17 -07:00
task.conf
Merge branch 'master' into ganesh_dev
2021-03-11 19:17:02 -07:00